Nahmsuk Oh

Error detection by selective procedure call duplication for low energy consumption

As commercial off-the-shelf (COTS) components are used in system-on-chip (SoC) design technique that is widely used from cellular phones to personal computers, it is difficult to modify hardware design to implement hardware fault-tolerant techniques and improve system reliability. Two major concerns of this paper are to: (a) improve system reliability by detecting transient errors in hardware, and (b) reduce energy consumption by minimizing error-detection overhead. The objective of this new technique, selective procedure call duplication (SPCD) is to keep the system fault-secured (preserve data integrity) in the presence of transient errors, with minimum additional energy consumption. The basic approach is to duplicate computations and then to compare their results to detect errors. There are 3 choices for duplicate computation: (1) duplicating every statement in the program and comparing results, (2) re-executing procedures through duplicated procedure calls, and comparing results, and (3) re-executing the whole program, and comparing the final results. SPDC combines choices (1) and(2). For a given program, SPCD analyzes procedure-call behavior of the program, and then determines which procedures can have duplicated statements [choice(1)] and which procedure calls can be duplicated [choice (2)] to minimize energy consumption with reasonable error-detection latency. Then, SPCD transforms the original program into a new program that can detect errors with minimum additional energy consumption by re-executing the statements or procedures. SPCD was simulated with benchmark programs; it requires less than 25% additional energy for error detection than previous techniques that do not consider energy consumption.

Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture

This paper proposes a new test compression technique that employs a fan-out scan chain with feedback (FSCANF) architecture. It allows us to use prelude vectors to resolve dependencies created by fanning out multiple scan chains from a single scan-in pin. This paper describes the new proposed architecture as well as the algorithm that generates compressed test vectors using a vertex coloring algorithm. The distribution of specified bits in each test pattern determines the compression ratio of the individual test pattern. Therefore, our technique optimizes the overall compression ratio and shows higher reduction in test data and application time than previous techniques, which use the extreme case of serializing all the scan chains in the presence of conflicts across the fanout scan chains. The FSCANF architecture has small hardware overhead and is independent of scan cell orders in the scan chains. Experimental results show that our technique significantly reduces both the test data volume and test application time in six of the largest ISCAS 89 sequential benchmark circuits compared to the previous techniques.

Fast seed computation for reseeding shift register in test pattern compression

Solving a system of linear equations has been widely used to compute seeds for LFSR reseeding to compress test patterns. However, as chip size is growing, solving linear equations requires a large number of computations that is proportional to n3. This paper proposes a new scan chain architecture and algorithm so that the order of computation is proportional to the number of scan cells in a chip. The new architecture is a methodology change that does not require complex Design-For-Testability (DFT) as proposed in the previous techniques. Instead of solving linear equations, the proposed new seed computation algorithm topologically determines seeds for test vectors. The compression ratio might be slightly lower than the other approaches, but the proposed approach can handle larger designs in a reasonable amount of time. Computation analysis shows that, for 1 million scan cell design, if we assume it takes 1 msec for the proposed technique to compute seeds, it would take more than 14 minutes for other techniques that solve linear equations.

Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback Loop

Noise glitches can cause functional errors or failures if they are latched into sequential cells. Thus it is very important to determine or characterize noise failure criteria of sequential cells. However, characterizing noise failure criteria of sequential cells is very computationally expensive because it often requires multiple transient simulations with different clock waveform shapes and alignments, known as clock sweeping. In this paper, we propose a new technique that eliminates the clock sweeping by using the meta-stable point of sequential cells. Our experiments with industrial circuits have shown that the proposed method is on average 58times faster than the conventional clock sweeping method and its average error is only 2.4%

Fast Crosstalk Repair by Quick Timing Change Estimation

Post route crosstalk repair is a difficult process and often requires significant manual intervention. Since repairing crosstalk for one net may cause new timing violations on other nets, the repair process might not converge. This often makes automation process of crosstalk repair difficult. In this paper, we formulate crosstalk repair process as an integer linear programming (ILP). Then, we propose a fast and efficient heuristic algorithm that minimizes the number of repairs by quickly estimating and predicting new timing information to choose the best candidate. Our experiments with industrial designs have shown excellent crosstalk repair results without any manual intervention