Peivand Tehrani

Deep sub-micron static timing analysis in presence of crosstalk

A complete and accurate method for static timing analysis of deep sub-micron devices in presence of crosstalk is introduced. This scheme provides an efficient platform for fast and accurate static timing verification of large scale transistor and cell level netlists, with coupled interconnects and high switching speeds. This paper presents the solution to the crosstalk problem implemented in the static timing tool PathMill as its crosstalk extension (CTX). A comparison of simulation results between this approach and SPICE is also provided.

Worst-case aggressor-victim alignment with current-source driver models

Crosstalk delay-noise which occurs due to the simultaneous transitions of victim and aggressor drivers is very sensitive to their mutual alignment. Hence, during static noise analysis, it is crucial to identify the worst-case victim-aggressor alignment which results in the maximum delay-noise. Although several approaches have been proposed to obtain the worst-case aggressor alignment, most of them compute only the worst-case stage delay of the victim. However, in reality it is essential to compute the worst-case combined delay of victim stage and victim receiver gate. We propose a heuristic approach to compute the worst-case aggressor alignment which maximizes the victim receiver output arrival time. In this work, we use a novel cumulative gate overdrive voltage (CGOV ) metric to model the victim receiver output transition. HSPICE simulations, performed on industrial nets to validate the proposed methodology, show an average error of 1.7% in delay-noise when compared to the worst-case alignment obtained by an exhaustive sweeping.

Crosstalk timing windows overlap in statistical static timing analysis

Process variation can have significant impact on device and interconnect performance, especially in the presence of crosstalk. A key technique to reduce crosstalk analysis pessimism is to consider timing window overlap of electrically coupled signals. SSTA timing windows tend to be larger than their corner counterparts resulting in pessimistic timing window overlap analysis, hence overestimating crosstalk impact. This paper describes an efficient method to remove die-to-die as well as common portion of within-die pessimism of the timing window overlap analysis. This approach has been implemented in an industrial timing analysis tool and experimental results show significant accuracy improvement and pessimism reduction compared to the existing techniques.

Fast Crosstalk Repair by Quick Timing Change Estimation

Post route crosstalk repair is a difficult process and often requires significant manual intervention. Since repairing crosstalk for one net may cause new timing violations on other nets, the repair process might not converge. This often makes automation process of crosstalk repair difficult. In this paper, we formulate crosstalk repair process as an integer linear programming (ILP). Then, we propose a fast and efficient heuristic algorithm that minimizes the number of repairs by quickly estimating and predicting new timing information to choose the best candidate. Our experiments with industrial designs have shown excellent crosstalk repair results without any manual intervention