Naim Ben-Hamida

A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory

Modern optical systems increasingly rely on DSP techniques for data transmission at 40Gbs and recently at 100Gbs and above. A significant challenge towards CMOS TX DSP SoC integration is due to requirements for four 6b DACs (Fig. 10.8.1) to operate at 56Gs/s with low power and small footprint. To date, the highest sampling rate of 43Gs/s 6b DAC is reported in SiGe BiCMOS process [1]. CMOS DAC implementations are constraint to 12Gs/s with the output signal frequency limited to 1.5GHz [2–4]. This paper demonstrates more than one order of magnitude improvement in 6b CMOS DAC design with a test circuit operating at 56Gs/s, achieving SFDR >30dBc and ENOB>4.3b up to the output frequency of 26.9GHz. Total power dissipation is less than 750mW and the core DAC die area is less than 0.6×0.4 mm2.

Advances in High-Speed DACs, ADCs, and DSP for Software Defined Optical Modems

We review digital-to-analog and analog-to-digital converters (DACs and ADCs), as well as digital signal processing (DSP) functions for software defined optical modems using rich modulation formats. These next generation optical transceivers will enable bit rates from 100 Gb/s to 400 Gb/s and 1 Tb/s.

Analysis and Modeling of the Phase Detector Hysteresis in Bang-Bang PLLs

All-digital bang-bang phase-locked-loops suffer from unwanted output spurs due to their non-linear behavior. The digital implementation of these PLLs often introduces extra delay which affects the performance of BBPLLs. This comes from the retiming and resampling of the digital data in the loop. In this work the phase detector hysteresis is investigated as a source for additional performance degradation. The jitter dependency on the loop parameters in the presence of hysteresis is analyzed, providing a new insight to be considered when designing for minimum jitter. This analysis provides a quick estimation of the deterministic jitter and the location of the spurious tones thus allowing the timing resolution of the PD to be determined. A new model for the BBPLL is also introduced that considers the non-ideality of the PD and its effect on the loop. To evaluate the performance, a time-amplifier is used to improve the resolution of the PD. Jitter and spurious tone of the BBPLL with TA assisted PD are then compared with those of a loop with a regular PD. The results show that the TAPD improves the performance by a factor of 3. The design and simulations have been done in a 32-nm CMOS technology.

Temporal epilepsy seizures monitoring and prediction using cross-correlation and chaos theory.

Temporal seizures due to hippocampal origins are very common among epileptic patients. Presented is a novel seizure prediction approach employing correlation and chaos theories. The early identification of seizure signature allows for various preventive measures to be undertaken. Electro-encephalography signals are spectrally broken down into the following sub-bands: delta; theta; alpha; beta; and gamma. The proposed approach consists of observing a high correlation level between any pair of electrodes for the lower frequencies and a decrease in the Lyapunov index (chaos or entropy) for the higher frequencies. Power spectral density and statistical analysis tools were used to determine threshold levels for the lower frequencies. After studying all five sub-bands, the analysis has revealed that the seizure signature can be extracted from the delta band and the high frequencies. High frequencies are defined as both the gamma band and the ripples occurring within the 60-120 Hz sub-band. To validate the proposed approach, six patients from both sexes and various age groups with temporal epilepsies originating from the hippocampal area were studied using the Freiburg database. An average seizure prediction of 30 min, an anticipation accuracy of 72%, and a false-positive rate of 0% were accomplished throughout 200 h of recording time.

A DFT Loopback Scheme for ADC ENOB Testing Using an All-Digital ATE

This article presents a design-for-test (DFT) loopback scheme for testing the analog portion of a mixed-signal chip using an all- digital tester. In fact, the proposed approach is used to assess the ENOB of a high-speed 6-bit ADC without the need for an external signal generator. Using an on-chip PLL with a programmable divider, a divided version of the 16GHz clock is passed through an on-chip buffer network where the output driver amplitude is programmable to achieve the desired fill ratio (~80%). The test PLL is coherent to the system PLL as they are driven from the same reference clock; hence, no windowing needs to be applied to the ADC output prior to performing the FFT for ENOB assessment. The on-chip output driver has an open-drain configuration that is far- end terminated through 50Ω pull-up resistors connected to a 2.0V external supply on the device interface board (DIB). The output is then applied to a 5th order external filter on the DIB with a 3dB cutoff frequency of 2.4GHz to filter out the high order harmonics prior to looping back the stimulus to the ADC front-end. The proposed scheme is implemented within a CMOS 32nm ADC macro and is experimentally validated using a commercial all-digital automated-test-equipment (ATE). A 4.5 bit ENOB was experimentally measured using the ADC under test. Unlike conventional loopback schemes, the proposed architecture is not susceptible to fault masking.

Frequency response of dual-drive silicon photonic modulators with coupling between electrodes

We characterize the electro-optic frequency response of a four-port traveling-wave dual-drive modulator with relatively strong coupling amongst the electrodes. We show that the electro-optic frequency response of the MZM can still be predicted with the 2×2 cascaded matrix model if the MZM is symmetric and differentially driven.

Programmable Active Clock Spine for 100Gb/200Gb Coherent Optical Receiver Chip in 32nm CMOS

This paper describes an active clock distribution network for a 100G/200G coherent optical receiver. The chip has more than 1 billion transistors implemented in 32nm CMOS bulk technology with 11 metal layers. The active clock spines enabled a low-skew, low jitter, and low power clock distribution solution. In addition, a debug-friendly clocking environment provides easy observability, testing, and reconfiguration features; hence, enabling rapid time to market.

A programmable analog frequency-locked loop for VCO characterization and test with 8 ppm resolution

This article presents a digitally controlled analog frequency-locked loop used for VCO characterization and test. The proposed scheme allows a frequency tuning better than 8 parts per million (ppm). The AFLL is implemented in 32nm CMOS technology and standard CMOS library cells are used for all the digital blocks. The AFLL comprises a 17-bit frequency counter running at 5GHz, a 1st order sigma-delta modulator used for dithering the correction signal, a charge-pump and capacitance used as integrator and a VCO. The frequency counter generates a count difference between the VCO clock and a reference clock. This difference is then pulse-density modulated and applied to a charge-pump feeding a capacitor that acts as an integrator. The generated output voltage is applied to the VCO tuning port and adjusts its oscillating frequency accordingly. An offset value added to the frequency difference allows the VCO to settle to a proportional frequency offset. Using this architecture, the VCO frequency can accurately be tuned digitally without having to change the frequency of a reference clock or sweeping its tuning voltage. Hence, the proposed AFLL can serve as a design-for-test (DFT) solution allowing characterization and testing of the VCO in an all-digital environment such as for digital automated test equipment (ATE).

A 32-nm CMOS Frequency Locked Loop for 20-GHz Synthesis with ± 7.6 ppm Resolution

In this work, a digitally assisted frequency locked loop is implemented using 32-nm CMOS technology and acts as a 20-GHz frequency synthesizer. The frequency difference between the reference clock and the VCO output is obtained using a pair of 18- bit counters. Also, an offset value is added to the counter output to tune the VCO frequency in closed loop. The frequency synthesizer resolution is ± 7.6 p.p.m. over a measured locking range equal to 300 MHz.