Wook-Je Kim

Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices

High-k/metal gate (HKMG) compatible high performance Source/Drain (S/D) stress-memorization-technology (SMT) is presented. Channel stress generated by SMT can be simulated by using mask-edge dislocation model, which is consistent with the measured actual channel stress. Extremely deep pre-amorphization-implant (PAI) for SMT creates multiple mask-edge dislocations under S/D region, which enhances short-channel mobility by 40∼60%. Finally, more than 10% short channel drive current gain is achieved with additional S/D extension optimization.

CMOS device scaling beyond 100 nm

CMOS device scaling beyond 100 nm has been investigated. Issues on scaling and previous works to solve them were reviewed. Super steep retrograde channel formation using selective epitaxial growth of undoped silicon effectively suppressed short channel effect and improved transconductance. The stack gate dielectrics of oxynitride and nitride suppressed boron penetration and improved drive currents. Transistor characteristics and reliability issues on gate oxide scaling were investigated in the regime of large gate leakage currents. High performance CMOS transistors of L/sub gate/=70 nm and T/sub ox/=1.4 nm were fabricated, which showed current drives of 860 /spl mu/A//spl mu/m (NMOS) and 350 /spl mu/A//spl mu/m (PMOS) at I/sub off/=10 nA//spl mu/m and V/sub dd/=1.2 V.

Fully Integrated Advanced Bulk FinFETs Architecture Featuring Partially-Insulating Technique for DRAM Cell Application of 40nm Generation and Beyond

For the first time, we have successfully fabricated fully integrated advanced bulk FinFETs featuring partially insulating oxide layers under source/drain (S/D), named partially-insulated- FinFETs (PI-FinFETs), to control subchannel on the bottom part of the gate in bulk FinFETs and suppress punchthrough and junction leakage currents. We observed that the junction leakage is improved about 50%, drain-induced barrier lowering (DIBL) about 25%, and lifetime of hot carrier effect (HCE) about 1 order in comparison with normal bulk FinFETs. Furthermore, we propose a novel PI-FinFET structure with pad-polysilicon side contact (PSC) in bulk-Si to reduce gate induced drain leakage (GIDL) and increase Ion with improved SCE immunity. The simulation of novel structure shows that Ion, DIBL and GIDL is improved dramatically with the same login comparison with bulk FinFETs. This advanced structure is suitable for the miniaturization of GIDL of bulk FinFETs with improved Ion, Ioff and DIBL characteristics

A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n/sup +/-doped polysilicon

Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully developed. A unique and simple DRAM technology with dual-gate CMOSFET was realized using plasma-nitrided thin gate oxide and p/sup +/ poly gate formed by BF/sub 2/ ion implanted compensation of in situ phosphorus (n/sup +/) doped amorphous silicon gate. Using this technology, boron penetration into the channel, gate poly depletion, and dopant interdiffusion between n/sup +/- and p/sup +/-doped WSi/sub x/-polycide gates were successfully suppressed. In addition, a negatively biased word line scheme and a storage capacitor with laminated high-/spl kappa/ Al/sub 2/O/sub 3/ and HfO/sub 2/ dielectrics were also developed to achieve mobile DRAM operating at 1.2 V with excellent performance and reliability.

On the gate oxide scaling of high performance CMOS transistors

The gate oxide scalability of high performance CMOS transistor has been investigated. In terms of gate leakage, the T/sub ox/ can be scaled down to at least 8 /spl Aring/ with I/sub G/ not exceeding I/sub off/ limit suggested by ITRS. To reduce boron penetration, remote-plasma-nitridation (RPN) oxides were studied. Devices with RPN oxides showed excellent resistance against boron penetration, improved hole mobility, reduced gate leakage, and improved transistor performance. The gate oxide scalability can be extended using the RPN process.

High performance pMOSFET with BF/sub 3/ plasma doped gate/source/drain and S/D extension

A BF/sub 3/ Plasma doping (PLAD) process has been utilized in source/drain/gate and shallow S/D extension for high performance 0.18 /spl mu/m pMOSFET. Gate oxide reliability, drain current, and transconductance of the pMOSFET with BF/sub 3/ PLAD are remarkably improved compared to those of BF/sub 2/ ion implanted devices. Cobalt salicide formation is also compatible with the plasma doped S/D junction.

A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond

A novel tensile Si (tSi) and compressive SiGe (cSiGe) dual-channel FinFET CMOS co-integration scheme, aimed at logic applications for the 5nm technology node and beyond, is demonstrated for the first time, showing electrical performance benefits and excellent co-integration feasibility. A Strain-Relaxed SiGe Buffer (SRB) layer is introduced as buried stressor and successfully transfers up to ∼1 GPa uniaxial tensile and compressive stress to the Si/SiGe n-/p-channels simultaneously. As the result, both tSi and cSiGe devices show a 40% and 10% electron and hole mobility gain over unstrained Si, respectively. Through a novel gate stack solution including a common interfacial layer (IL), HK, and single metal gate for both n- and pFET, secured process margin for 5nm gate length, low interface trap density (Dit) for SiGe channel and threshold voltage (Vt) target for both the Si and SiGe device are successfully demonstrated. Lastly, reliability investigation shows that tSi and cSiGe, employing the newly developed common gate stack scheme, possess superior reliability characteristics compared with those of equivalent Si devices.

Scalable Two-Transistor Memory (STTM)

A novel memory device called Scalable Two-Transistor Memory (STTM) has been developed. STTM is a floating gate device with the writing mechanism of direct tunneling through the multiple tunnel junction (MTJ). STTM has potential advantages of scalability, high density, high speed, long data retention, low voltage operation, low power consumption, and good endurability. We have fabricated and successfully demonstrated the memory cell operation of the STTM for the first time. The STTM unit cell fabricated using 0.16 /spl mu/m silicon processing showed the writing speed of /spl sim/100 ns and the data retention time of /spl sim/200 sec. with the operation voltages of -5/spl sim/5 V. Also, we developed a novel architecture for the high-density STTM cell array with an unit cell size of 4F/sup 2/ and a process scheme to fabricate it.

A Novel Body Effect Reduction Technique to Recessed Channel Transistor Featuring Partially Insulating Layer Under Source and Drain : Application to Sub-50nm DRAM Cell

We have successfully fabricated fully integrated advanced RCAT (Recess Channel Array Transistor) featuring partially insulating oxide layers in bulk Si substrate, named Partially-insulated-RCAT (Pi-RCAT) to suppress body effect of conventional RCAT and improve current drivability in DRAM cell. The Pi-RCAT demonstrated superior characteristics in body effect, subthreshold slope (SW) and higher current drivability with comparable Ion-Ioff characteristics in comparison with conventional RCAT. Furthermore, in the partially-insulated-STI (Pi-STI) of core and peripheral structure formed simultaneously, well isolation characteristic is improved remarkably due to increase of effective isolation path. In this paper, Pi-RCAT is proved to be effective for the scalability and drivability of RCAT, and Pi-STI is suitable for the improvement of chip shrinkage efficiency.

Drain leakage fluctuation reduction in the recessed channel array transistor DRAM with the elevated source-drain

Gate induced drain leakage (GIDL) characteristics were investigated with the recessed channel array transistor (RCAT) for DRAM, using the elevated source drain (ESD). The lower doping concentration of a source-drain region in the ESD structure reduces the electric field, which reduces drain leakage current and also the fluctuation of leakage current. These reductions can enhance the data retention time of DRAM. The reduced electric field also improves hot carrier immunity of the cell transistor as well.