Namiko Ikeda

Fingerprint image enhancement by pixel-parallel processing

This paper proposes a fingerprint image enhancement algorithm that can be mapped onto a compact pixel-parallel architecture, such as a fingerprint identification chip that senses and identifies fingerprints by itself. The algorithm is composed of two parts. First, ridges are enhanced by extracting their center lines and removing white noises using the center line image. Then valleys are enhanced by detecting areas where they are thin and disconnected and dilating them at these areas. Both enhancements are done with the structures of the fingerprint maintained. The experimental results show fingerprint identification using the proposed image enhancement algorithm improves the error ratio of that the conventional method, and the execution time is 0.14 msec when the proposed algorithm is performed on the array of processing elements on the fingerprint identification chip.

A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification

A 500-dpi cellular-logic processing array performs all fingerprint identification steps on one chip, from image acquisition, enhancement, to verification. Morphological functions for executing these steps are implemented in a 30/spl times/50-/spl mu/m/sup 2/ processing unit. A single-cycle datapath and a shared logic structure enable compact implementation of the processing unit. A fabricated 224/spl times/256-pixel fingerprint identification LSI demonstrates fully-functional image processing and practical accuracy of identification.

Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier

This paper presents fingerprint image enhancement and rotation schemes that improve the identification accuracy with the pixel-parallel processing of pixels. In the schemes, the range of the fingerprint sensor is adjusted to the finger state, the captured image is retouched to obtain the suitable image for identification, and the image is rotated to the correct angle on the pixel array. Sensor and pixel circuits that provide these operations were devised and a test chip was fabricated using 0.25-μm CMOS and the sensor process. It was confirmed in 150,000 identification tests that the schemes reduce the false rejection rate to 6.17% from 30.59%, when the false acceptance rate is 0.1%.

Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI

This paper describes logic and analog test schemes that improve the testability of a pixel-parallel fingerprint identification circuit. The pixel contains a processing circuit and a capacitive fingerprint sensor circuit. For the logic test, we propose a test method using a pseudo scan circuit to check the processing circuits of all pixels simultaneously. In the analog test, the sensor circuit employs dummy capacitance to mimic the state of a finger touching the chip. This enables an evaluation of the sensitivity of all sensor circuits on logical LSI tester without touching the chip with a finger. To check the effectiveness of the schemes, we applied them to a pixel array in a fingerprint identification LSI. The pseudo scan circuit achieved a 100% failure-detection rate for the processing circuit. The analog test determines that the sensitivities of the sensor circuit in all pixels are in the proper range. The results of the tests confirmed that the proposed schemes can completely detect defects in the circuits. Thus, the schemes will pave the way to logic and analog tests of chips integrating highly functional devices stacked on a LSI.

High-speed sorted-table search scheme for network processing

We propose a scheme for quickly completing a sorted-table search, which is one of most common searches employed in network processing. In the scheme, the range to be searched is narrowed using only a simple calculation. This narrowing is incorporated into conventional search procedures such as binary search. Simulation results show that our proposed approach reduces the number of times element values are read from the table, which results in faster search.

Isolator-free EA-DFB module with forward error correction

We offer an isolator-free EA-DFB module by employing forward error correction. We analyze the behavior of a laser under optical feedback and the error occurrence mechanism. We obtain error-free operation at the receiver sensitivity of -31 dBm.

Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs

Verification of the hardware/software functions of a 10-Gbit/s-class large-scale network systems-on-a-chip (NW SoC) requires the use of multiple field programmable gate array (FPGA) devices. We propose two schemes for the efficient mapping of the design data of the NW SoC into FPGA devices. We implemented practical NW SoC design data for FPGA devices, and evaluated the effectiveness of the schemes. The results show that the proposed schemes can reduce the number of wires by 13% and improve the register access cycle time by 28%.