Naohiro Hamada

A tool set for the design of asynchronous circuits with bundled-data implementation

This paper proposes a tool set for the design of asynchronous circuits with bundled-data implementation. Using the proposed tool set with commercial CAD tools, asynchronous circuits with bundled-data implementation can be designed easily. Through the experiments, this paper evaluates synthesized circuits using the proposed tool set in terms of area, performance, power consumption, and energy consumption comparing with synchronous counterparts.

A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs

This paper proposes a floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. The proposed method minimizes the delay of the control circuit while considering timing constraints required for bundled-data implementation. Through the implementation of the proposed method, this paper evaluates the proposed method in terms of performance and area for generated floorplans.

Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times

This paper proposes new scheduling methods for asynchronous circuits with bundled-data implementations. Since operations in asynchronous circuits start after the completion of a previous operation, this method approximates the set of start times for each operation using the delay of the resources. Next, this method decides on control steps from the approximated sets of start times, which are used in scheduling algorithms. This paper extends two scheduling algorithms used for synchronous circuits so that the approximated sets of start times and the decided control steps are used. Finally, this paper shows the effectiveness of our proposed methods by comparing scheduling results with ones obtained by the original two scheduling algorithms.

A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper)

This paper presents a behavioral synthesis method for asynchronous circuits with bundled-data implementation. This paper extends a behavioral synthesis method for synchronous circuits so that an RTL model of bundled-data implementation is synthesized from a behavioral description specified by a restricted C language. Finally, this paper evaluates our method for several benchmarks through a tool implementation.

A Control Circuit Synthesis Method for Asynchronous Circuits in Bundled-Data Implementation

This paper proposes a control circuit synthesis method for asynchronous circuits in bundled-data implementation. Our proposed method consists of the synthesis of a control circuit to control a data-path circuit and the synthesis of an interface circuit between the control circuit and the data-path circuit. The control circuit is generated by mapping small control elements called Q-elements. For mapping, this paper proposes two mapping methods called the state-oriented mapping method and the node-oriented mapping method. Finally, this paper shows the effectiveness of the proposed method by comparing synthesized circuits with ones obtained by a different control circuit synthesis method.

Integration of behavioral synthesis and floorplanning for asynchronous circuits with bundled-data implementation

In this paper, we propose a synthesis method for asynchronous circuits with bundled-data implementation which iteratively applies behavioral synthesis and floorplanning to obtain an optimum circuit in terms of performance under given design constraints. We evaluate the effectiveness of the proposed method through synthesizing several benchmarks. Experimental results show that the proposed method synthesizes faster circuits compared to ones without considering timing constraints. Also, the proposed method is effective to reduce the number of timing violations.