Naohiro Harigai

CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation

This paper describes a reference-clock-free, high-time-resolution on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier (TDA) with duty-cycle compensation. A self-referenced clock with multiples of the clock period removes the necessity for a reference clock. In addition, a cascaded TDA with duty-cycle compensation improves the time resolution while maintaining the operational speed. Test chips were designed and fabricated using 65 nm and 40 nm CMOS technologies. The areas occupied by the circuits are 1350 μm2 (with TDA, 65 nm), 490 μm2 (without TDA, 65 nm), 470 μm2 (with TDA, 40 nm), and 112 μm2 (without TDA, 40 nm). Time resolutions of 31 fs (with TDA) and 2.8 ps (without TDA) were achieved. The proposed new architecture provides all-digital timing jitter measurement with fine-time-resolution measurement capability, without requiring a reference clock.

Phase noise measurement techniques using delta-sigma TDC

This paper describes two techniques for measuring phase noise of a clock using a delta-sigma time-to-digital converter (TDC). One technique uses a reference signal (which has only very small phase noise), and the other does not use a reference signal. Both proposed techniques can be implemented with relatively simple circuitry, due to the following: (i) The clock under test (CUT) is a repetitive signal. (ii) The time resolution with CUT and a reference clock can be increased by using longer measurement time with the delta-sigma TDC. (iii) The phase noise power spectrum can be calculated from the delta-sigma TDC output data using FFT. Costly high-performance spectrum analyzers which average several-time phase measurement results over a long measurement time (about 10s order), are not needed for phase noise measurement with the proposed technique. The other technique, which differs in that it uses a self-referenced clock rather than a reference signal, has potential wide applications.

A clock jitter reduction circuit using gated phase blending between self-delayed clock edges

A clock jitter reduction circuit is presented that exploits the phase blending technique between the uncorrelated clock edges that are self-delayed by multiples of the clock cycle, nT. By blending uncorrelated clock edges, the output clock edges approach the ideal timing and, thus, timing jitter can be reduced by a factor of √2 per stage. There are three technical challenges to realize this: 1) generating uncorrelated clock edges, 2) phase averaging with small time offset from the ideal center position, and 3) minimizing the error in nT-delay being deviated from ideal nT. The proposed circuit overcomes each of these by exploiting an nT-delay, gated phase blending, and self-calibrated nT-delay elements, respectively. Measurement results with a 180-nm CMOS prototype chip demonstrated an approximately fourfold reduction in timing jitter from 30.2 ps to 8.8 ps in 500-MHz clock by cascading the proposed circuit with four-stages.

Design methodology for determining the number of stages in a cascaded time amplifier to minimize area consumption

This paper describes a design methodology for determining the number of stages in a cascaded time amplifier to minimize the area consumption. The total area consumption is categorized into three parts, which allows mathematical analysis and optimization to be performed. A combination of the proposed mathematical analysis and 2D mapping can determine the number of stages to minimize the area consumption.

An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation

This paper demonstrates a reference-free, high-resolution on-chip timing jitter measurement circuit. It combines a self-referenced clock and a cascaded time difference amplifier (TDA) with duty-cycle compensation, which results in reference-free, high-resolution timing jitter measurement without sacrificing operational speed. The test chip was designed and fabricated in 65 nm CMOS. Measured results of the proposed circuit show the possibility of detecting a timing jitter of 1.61-ps RMS in 820 MHz clock with less than 4% error.

A CMOS PWM Transceiver Using Self-Referenced Edge Detection

A CMOS pulsewidth modulation (PWM) transceiver circuit that exploits the self-referenced edge detection technique is presented. By comparing the rising edge that is self-delayed by about 0.5 T and the modulated falling edge in one carrier clock cycle, area-efficient and high-robustness (against timing fluctuations) edge detection enabling PWM communication is achieved without requiring elaborate phase-locked loops. Since the proposed self-referenced edge detection circuit has the capability of timing error measurement while changing the length of self-delay element, adaptive data-rate optimization and delay-line calibration are realized. The measured results with a 65-nm CMOS prototype demonstrate a 2-bit PWM communication, high data rate (3.2 Gb/s), and high reliability (BER> 10-12) with small area occupation (540 μm2). For reliability improvement, error check and correction associated with intercycle edge detection is introduced and its effectiveness is verified by 1-bit PWM measurement.

A low-offset cascaded time amplifier with reconfigurable inter-stage connection

This study demonstrates the design and testing of a reconfigurable cascaded time amplifier (TA) that enables a reduction in the output offset. By testing the polarity of the output offset time caused by process variations in each stage and then reconfiguring the inter-stage connections, we find that the total output offset time can be reduced dramatically. The results of a SPICE simulation of a 65-nm CMOS match well with the theoretical estimates and show the effectiveness of this proposed testing structure and reconfigurable inter-stage connection technique.

Phase Noise Measurement and Testing with Delta-Sigma TDC

This paper describes a phase noise measurement and testing technique for a clock using a delta-sigma time-to-digital converter (TDC) and verifies its effectiveness with MATLAB simulations. The proposed technique can be implemented with relatively small circuitry, based on the following: (i) The clock under test (CUT) is a repetitive signal. (ii) The time resolution with CUT and a reference clock can be finer with longer measurement time with the delta-sigma TDC. (iii) The phase noise power spectrum can be calculated from the delta-sigma TDC output data using FFT. High performance spectrum analyzers with long measurement time (several ten seconds order due to average of several-time phase measurement results), which are very costly in mass production testing, are not be needed for phase noise measurement with the proposed technique. Our simulation used the input clock of 1 MHz in several phase fluctuation cases, and we observed that the phase fluctuation spectrum at the expected frequency from TDC output power spectrum obtained by FFT. We also investigated the amount of phase fluctuation with our theoretical calculation, which agrees with the simulation results.

Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges

Design of a clock jitter reduction circuit that exploits the phase blending technique between the uncorrelated clock edges that are self-delayed by multiples of the clock cycle, nT is presented. By blending uncorrelated clock edges, the output clock edges approach the ideal timing and, thus, timing jitter can be reduced by a factor of √2 per stage. There are three technical challenges to realize this: 1) generating uncorrelated clock edges, 2) phase averaging with small time offset from the ideal center position, and 3) minimizing the error in nT-delay being deviated from ideal nT. The proposed circuit overcomes each of these by exploiting an nT-delay, gated phase blending, and self-calibrated nT-delay elements, respectively. Measurement results with a 180-nm CMOS prototype chip demonstrated an approximately four-fold reduction in timing jitter from 30.2 ps to 8.8 ps in 500-MHz clock by cascading the proposed circuit with four-stages.

Design Methodology and Jitter Analysis of a Delay Line for High-Accuracy On-Chip Jitter Measurements

This work presents the design methodology and jitter analysis of a delay line for high-accuracy on-chip jitter measurements. Jitter generated in the delay lines degrades the accuracy of on-chip jitter measurements, and required to be minimized. In order to analyze and the jitter generation in the delay lines, SPICE simulation was performed with 65 nm CMOS technology. Simulation results show that jitter due to thermal noise can be reduced by enlarging the transistor sizes of both PMOS and NMOS. Based on the results, design methodology of a delay line is introduced for minimizing the jitter generation.