Kiichi Niitsu

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30mum. The total layout area is 2mm2 in 0.18mum CMOS and the chip thickness is 10mum. 4-phase TDMA reduces crosstalk and the BER is <10minus;12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link

A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 mum in a layout area of 1 mm2. The total layout area including 16 clock transceivers is 2 mm2 in 0.18 mum CMOS and the chip thickness is reduced to 10 mum. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10-13

A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna

This paper presents a novel impulse radio based ultra-wideband transmitter. The transmitter is designed in 0.18 mum CMOS process realizing extremely low complexity and low power. It exploits the 6-to-10 GHz band to generate short duration bi-phase modulated UWB pulses with a center frequency of 8 GHz. No additional RF filtering circuits are required since the pulse generator circuit itself has the functionality of pulse shaping. Generated pulses comply with the FCC spectral emission mask. Measured results show that the transmitter consumes 12 pJ/b to achieve a maximum pulse repetition rate of 750 Mb/s. An optional embedded on-chip antenna and a power amplifier operating in 6-10 GHz band are also designed and investigated as a future low cost solution for very short distance IR-UWB communications.

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM

This paper presents a three-dimensional (3D) system integration of a commercial processor and a memory by using inductive coupling. A 90nm CMOS 8-core processor, back-grinded to a thickness of 50µm, is mounted face down on a package by C4 bump. A 65nm CMOS 1MB SRAM of the same thickness is glued on it face up, and the power is provided by conventional wire-bonding. The two chips under different supply voltages are AC-coupled by inductive coupling that provides a 19.2Gb/s data link. Measured power and area efficiency of the link is 1pJ/b and 0.15mm2/Gbps, which is 1/30 and 1/3 in comparison with the conventional DDR2 interface respectively [1]. The power efficiency is improved by narrowing a transmission data pulse to 180ps. Reduced timing margin for sampling the narrow pulse, on the other hand, is compensated against timing skews due to layout and PVT variations by a proposed 2-step timing adjustment using an SRAM through mode. All the bits of the SRAM is successfully accessed with no bit error under changes of supply voltages (±5%) and temperature (25°C, 55°C).

A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping

A transceiver for inductive-coupling is realized. By using a pulse-shaping circuit, the transmitter energy is 0.11 pJ/b. Due to device scaling from 180 nm CMOS to 90 nm CMOS, the receiver energy is 0.03 pJ/b. The overall energy dissipation is 20X lower than previous work, without degrading the data rate of 1 Gb/s.

Amperometric electrochemical sensor array for on-chip simultaneous imaging

We propose an amperometric electrochemical sensor array for high-speed measurement of microelectrode currents. The biosensor was fabricated using CMOS technology and a contact photolithographic process to incorporate gold microelectrodes (256 electrodes) on a chip. The sensor circuit employed a current buffer circuit and dual switch. During measurement, all electrodes were kept at a constant potential, currents were at steady-state levels, and rapid switching was performed while maintaining the steady-state current. The measured current range of the current buffer circuit was approximately 1 pA to 1 µA. A microelectrode array (MEA) with auxiliary electrode (AE) was used to suppress expansion of the diffusion layer over the MEA. Steady-state current was obtained and amplified by redox cycling, greatly reducing the time for reaching the steady-state level. The sensor successfully simultaneously measured multipoint cyclic voltammetry and amperometry, and will be useful for measuring local concentration and analyzing the diffusion processes of target molecules.

Development of Microelectrode Arrays Using Electroless Plating for CMOS-Based Direct Counting of Bacterial and HeLa Cells

The development of two new types of high-density, electroless plated microelectrode arrays for CMOS-based high-sensitivity direct bacteria and HeLa cell counting are presented. For emerging high-sensitivity direct pathogen counting, two technical challenges must be addressed. One is the formation of a bacteria-sized microelectrode, and the other is the development of a high-sensitivity and high-speed amperometry circuit. The requirement for microelectrode formation is that the gold microelectrodes are required to be as small as the target cell. By improving a self-aligned electroless plating technique, the dimensions of the microelectrodes on a CMOS sensor chip in this work were successfully reduced to 1.2 μm × 2.05 μm. This is 1/20th of the smallest size reported in the literature. Since a bacteria-sized microelectrode has a severe limitation on the current flow, the amperometry circuit has to have a high sensitivity and high speed with low noise. In this work, a current buffer was inserted to mitigate the potential fluctuation. Three test chips were fabricated using a 0.6- μm CMOS process: two with 1.2 μm × 2.05 μm (1024 × 1024 and 4 × 4) sensor arrays and one with 6- μm square (16 × 16) sensor arrays; and the microelectrodes were formed on them using electroless plating. The uniformity among the 1024 × 1024 electrodes arranged with a pitch of 3.6 μm × 4.45 μm was optically verified. For improving sensitivity, the trenches on each microelectrode were developed and verified optically and electrochemically for the first time. Higher sensitivity can be achieved by introducing a trench structure than by using a conventional microelectrode formed by contact photolithography. Cyclic voltammetry (CV) measurements obtained using the 1.2 μm × 2.05 μm 4 × 4 and 6- μm square 16 × 16 sensor array with electroless-plated microelectrodes successfully demonstrated direct counting of the bacteria-sized microbeads and HeLa cells.

CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation

This paper describes a reference-clock-free, high-time-resolution on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier (TDA) with duty-cycle compensation. A self-referenced clock with multiples of the clock period removes the necessity for a reference clock. In addition, a cascaded TDA with duty-cycle compensation improves the time resolution while maintaining the operational speed. Test chips were designed and fabricated using 65 nm and 40 nm CMOS technologies. The areas occupied by the circuits are 1350 μm2 (with TDA, 65 nm), 490 μm2 (without TDA, 65 nm), 470 μm2 (with TDA, 40 nm), and 112 μm2 (without TDA, 40 nm). Time resolutions of 31 fs (with TDA) and 2.8 ps (without TDA) were achieved. The proposed new architecture provides all-digital timing jitter measurement with fine-time-resolution measurement capability, without requiring a reference clock.

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link

MuCCRA-Cube is a scalable three dimensional dynamically reconfigurable processor. By stacking multiple dies connected with inductive-coupling links, the number of PE array can be increased so that the required performance is achieved. A prototype chip with 90nm CMOS process consisting of four dies each of which has a 4 × 4 PE array was implemented. The vertical link achieved 7.2Gb/s/chip, and the average execution time is reduced to 31% compared to that using a single chip.

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link

This paper describes a three-dimensional (3-D) system integration of a full-fledged processor chip and two memory chips using inductive coupling. To attain a 3-D communication link with a smaller area and lower power-consumption, shortening the link distance and preventing signal degradation due to unused inductors are important challenges. Therefore, we developed a new 3D-integrated wire-penetrated multi-layer structure for a shorter link distance and an open-skipped-inductor scheme for suppressing signal degradation. In addition, to avoid undefined-value propagation in stacking multi-memories using an inductive-coupling link, we proposed a memory-access-control scheme with a pinpoint-data-capture scheme. We demonstrate that three fabricated chips can be successfully AC-coupled using inductive coupling. The power and area efficiency of the link are 1 pj/b and 0.15 mm2 /Gbps, respectively, which are the same as those of two-chip integration.