Nobukazu Takai

SAR ADC algorithm with redundancy

This paper describes a redundant algorithm for a highly reliable Successive Approximation Register (SAR) ADC where mistakes of comparator decision can be digitally-corrected. We generalize a conventional non-binary search algorithm which requires more conversion steps in the SAR ADC than the binary search algorithm, and clarify which decision errors can be digitally-corrected with the derived redundant algorithm. We also shows that the sampling speed of the SAR ADC using the proposed algorithm can be faster when the incomplete settling effects of the DAC inside the SAR ADC are taken into account.

Stochastic TDC architecture with self-calibration

This paper describes a time-to-digital converter (TDC) architecture with fine time resolution, self-calibration and self-testing, and these features are realized by the following: (1) Encoder circuit that ensures monotonic characteristics. (2) Self-calibration circuit for linearity improvement. (3) Stochastic architecture for fine time resolution. (4) Self-testing for reliability requirements. These features can be implemented with an advanced fine CMOS process using digital design methodology. The circuit structure and operation are described, and MATLAB simulation results are presented.

Non-binary SAR ADC with digital error correction for low power applications

This paper describes techniques for creating a low-power SAR ADC with an error-correcting non-binary successive approximation algorithm; it is suitable for low power applications, performs digital error correction, and does not require analog calibration. Two techniques have been proposed for implementing low-power SAR ADCs: use of two comparators, and a charge-sharing architecture. However these techniques would normally require analog calibration of comparator offsets. Here we propose a non-binary SA algorithm that compensates for comparator offset effects in the digital domain, and so eliminates the need for analog calibration. Results of our Matlab simulation validate the effectiveness of this approach.

ADC linearity test signal generation algorithm

This paper describes an algorithm for generating test signals to efficiently test the linearity of ADCs. Linearity is an important testing item for ADCs, and it takes a long time (hence is costly) to test low-sampling-rate, high-resolution ADCs. We here propose to generate a test signal consisting of multiple sine waves, to precisely test the linearity for specific important codes (such as around the center of the output codes), using an arbitrary waveform generator (AWG) and an analog filter. We have performed MATLAB simulation to validate our algorithm, and the results show that in some cases the testing time can be reduced to half that for conventional sine wave histogram testing.

New architecture for envelope-tracking power amplifier for base station

This paper proposes a new architecture for envelope-tracking power supplies for base stations. The proposed multiphase DC-DC converter circuit uses multiple switching circuits (as well as a voltage follower circuit), each optimized for a different envelope frequency, to realize both high efficiency and wide bandwidth. The operation of the circuit, and simulation results, are described.

Multi-bit Sigma-Delta TDC Architecture with Improved Linearity

This paper describes the architecture and principles of operation of sigma-delta ( ΣΔ) time-to-digital converters (TDC) for high-speed I/O interface circuit test applications. In particular, we describe multi-bit ΣΔ TDC architectures; they offer good accuracy with short testing time. However, mismatches among delay cells in delay lines degrade their linearity. Here we propose two methods to improve the overall TDC linearity: a data-weighted-average (DWA) algorithm, and a self-calibration method that measures delay values using a ring oscillator circuit. Our Matlab simulation results demonstrate the effectiveness of these approaches.

A Time-to-Digital Converter with small circuitry

A Time-to-Digital-Converter (TDC) is to measure the interval time between two signals, and its time resolution of several pico seconds is achieved when it is implemented with advanced CMOS process [1–5]. Its applications are gradually expanding such as a phase comparator of all-digital-PLL, a sensor interface circuit, modulation circuit and demodulation circuit as well as a TDC-based ADC [1–6]. The TDC will play more important role in nano-CMOS era because it is well-matched to implement with fine digital CMOS process; it consists of mostly digital circuits, and as the switching speed increases, its performance is improved.

Single inductor dual output DC-DC converter design with exclusive control

This paper proposes a single inductor dual output (SIDO) DC-DC Converter with exclusive control circuit. We propose two kinds of converter: a buck-buck and a boost-boost converter. Multiple voltage outputs are controlled exclusively, using error voltage feedback. This approach requires few additional components (a switch, a diode and a comparator), requires no current sensors and does not depend on the value of output voltage or output current. We describe circuit topologies, operation principles and simulation results.

SAR ADC that is configurable to optimize yield

This paper describes a non-binary SAR ADC architecture that is reconfigurable at production testing time to increase the number of chips that meet a given sampling speed specification, i.e. to improve yield. A non-binary SAR ADC can realize higher sampling rates than a comparable conventional binary SAR ADC, by using overlapping SA ranges so that any errors due to incomplete settling of the internal DAC can be corrected in later steps of the successive approximation. In general, using more of the overlapping successive- approximation (SA) steps (and faster steps) permits faster SAR ADC sampling rates but increases power consumption. Thus this power-speed tradeoff can be utilized to compensate for CMOS process variations of each ADC chip; if the chip is slow, we can use more-rapid SA steps and more overlapping steps to satisfy the sampling speed specification (at the cost of increasing power consumption); if the chip is fast, we can use fewer (and slower) steps to satisfy the sampling speed specification and also achieve lower power consumption. We use automatic test equipment (ATE) for production testing and to store the appropriate algorithm data that enables the sampling rate specification to be met in flash memory on the chip. The DAC output settling margin is determined by checking comparator output at each step and confirming that ADC final output is correct. Our measurements demonstrate the effectiveness of this approach.

An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators

This paper presents a theoretical analysis of the stochastic calibration of TDC using two ring oscillators. Designers of TDC with the calibration function have to decide the design parameters to guarantee the convergence of error and valid calibration time. The basic theory of the calibration is useful to decide these parameters and the policy on the calibration design. The performance of the stochastic calibration depends on the design parameters, the frequencies of the two ring oscillators, the number of the stages, the buffer delay, and so on. This work analyzes explicitly the relation between these parameters and the performance of the calibration with simulation-based analysis. Simulation results reveal that the convergence of the calibration is guaranteed when both of the cycles of the two ring oscillators are the prime cycles. The histogram of each bin converges to the corresponding buffer delay value in a well-behaved manner, the DNL measurement error decreases monotonically in proportion to the increase of the number of the times of the measurement. In other words, the required number of the measurement times is in proportion to the required accuracy of calibration. This result is applied to the calibration of VDL-based TDC, too.