Naoji Senba

Three-dimensional memory module

Demand has recently increased for high packaging density and memory capacity of memory modules for electronic equipment. The new three-dimensional memory module satisfies this demand. This module has almost the same size as single memory packages [thin small outline packages (TSOPs): 17.4/spl times/9.22/spl times/1.2 mm] currently being used, and a package density four times as large. Electrical performance is better than that of TSOPs because the length of the wires is about half that of the TSOPs wires. Moreover, the cost of fabrication of this module is low. This paper reports the modules characteristics and fabrication process. The design concept is that next-generation memory devices will be produced by using current mass-produced memory devices.

3-dimensional memory module

Demand has recently increased for high packaging density and memory capacity of memory modules for electronic equipment. Our new 3-Dimensional Memory (3DM) Module satisfies this demand. This module has almost the same size as single memory packages (TSOPs: 17.4/spl times/9.22/spl times/1.2 mm) currently being used, and a package density 4 times as large. Electrical performance is better than that of TSOPs because the length of its wires is about half that of TSOPs wires. Moreover, the cost to fabricate this module is low. This paper reports the modules characteristics and fabrication process. The design concept is that next-generation memory devices will be produced by casing current mass-produced memory devices.

A silicon-on-silicon packaging technology for advanced ULSI chips

A RISC (reduced instruction set computer) module for high-performance workstations has been made to demonstrate the advantages and technical feasibility of the silicon-on-silicon technology. The module consists of one 0.8-/spl mu/m CMOS CPU (central processing unit) one 0.8-/spl mu/m CMOS FPU, and six 1.0-/spl mu/m BiCMOS cache memories. The eight chips are attached on a 39/spl times/47 mm square silicon substrate with 120-/spl mu/m pitch flip chip bonding of 80-/spl mu/m-diameter tin-lead bumps. Two-layer interconnections for high-speed signals are formed with 20-/spl mu/m line and 80-/spl mu/m space on the silicon substrate. The conductors are 4-/spl mu/m thick gold formed by electroplating and the dielectric film is 10-/spl mu/m-thick polyimide. A decoupling capacitance of about 0.8 nF is formed in the substrate. The module was evaluated using reliability and functional tests. The reliability tests included thermal cycling, power cycling, and mechanical strength tests. The functional test was carried out by connecting the module to an IBM-PC/IF board and operating with a test program. Both evaluations were successful.<<ETX>>

The ferrite-embedded drop-in circulator for millimeter wave communication systems

We have developed a ferrite-embedded drop-in circulator (FEC) that operates on the W-band for millimeter wave communication systems. The FEC is taken as the composite structure, that is, the Sr-ferrite disc is embedded in a dielectric layer which is formed on an alumina substrate. The FEC does not require a magnet by using the large anisotropy field, H/sub a/ of Sr-ferrite. And the FEC has a high flexural strength and has a coefficient of thermal expansion (CTE) similar to that of ceramic materials which are used for a multi-chip radio frequency (RF) module. As a result, the FEC can be assembled directly on multi-chip RF module. Moreover, benzocyclobutene (BCB), an organic resin, is the material used in the dielectric layer of the FEC. Using organic resins like BCB in the dielectric layer makes the process of embedding ferrite easy and simplifies fabrication. BCB also offers other advantages such as low dielectric loss, low moisture absorption, and excellent planarization. The optimumly configured FEC performed well, demonstrating an insertion loss of less than 2 dB, a return loss of more than 20 dB, and an isolation of more than 25 dB at 60 GHz. Using the MCM with the FEC directly assembled. Millimeter wave communications equipment are expected to have less than a tenth volume of conventional equipment and also to decrease in cost.

The Interface Reactions of Cu and Ni with Pb/Sn Solder

Cu and Ni as barrier metals have been investigated with respect to the interface reaction between the barrier metal and Pb/Sn (=40/60, 95/5 wt.%) solder. After storage tests at 100˜150 °C for 0˜3000hr, cross-sectional observations and analyses were carried out with SEM, WDX and EDX. As the results, the activation energies for Cu-Sn, Ni-Sn alloy formation and the life times of barrier metals Cu, Ni were obtained. Applying this work, the thicknesses of barrier metals Cu and Ni, which have in general been decided by trial and error methods, can be designed by calculation.