Koji Soejima
Renesas Electronics
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Publication
Featured researches published by Koji Soejima.
international interconnect technology conference | 2009
Yoichiro Kurita; Norikazu Motohashi; Satoshi Matsui; Koji Soejima; Shuhei Amakawa; Kazuya Masu; Masaya Kawano
We have developed a 3-D packaging technology called SMAFTI (SMArt chip connection with FeedThrough Interposer), which enables the implementation of a new memory/logic-interconnect hierarchy. Through experiments, we were able to confirm practical performance of this technology. We implemented a new die bonding process and the multilayer interconnect technology to form over a thousand parallel interconnects between memory and logic dies. Implementation of the new process was achieved with high productivity and low process costs. We characterized the interlaminar horizontal wiring by S-parameter measurement up to 40 GHz and confirmed its potential for high-speed signal transmission at over 10 Gb/s.
Archive | 2006
Katsumi Kikuchi; Shintaro Yamamichi; Yoichiro Kurita; Koji Soejima
Archive | 2006
Katsumi Kikuchi; Shintaro Yamamichi; Yoichiro Kurita; Koji Soejima
Archive | 2007
Nobuaki Takahashi; Masahiro Komuro; Koji Soejima; Satoshi Matsui; Masaya Kawano
Archive | 2006
Shintaro Yamamichi; Katsumi Kikuchi; Yoichiro Kurita; Koji Soejima
Archive | 2010
Masaya Kawano; Koji Soejima; Nobuaki Takahashi; Yoichiro Kurita; Masahiro Komuro; Satoshi Matsui
Archive | 2011
Nobuaki Takahashi; Masahiro Komuro; Koji Soejima; Satoshi Matsui; Masaya Kawano
Archive | 2011
Masaya Kawano; Koji Soejima
Electrochemistry | 2009
Yoichiro Kurita; Norikazu Motohashi; Satoshi Matsui; Koji Soejima; Shuhei Amakawa; Kazuya Masu; Masaya Kawano
Archive | 2006
Yoichiro Kurita; Masaya Kawano; Koji Soejima
