Tadanori Shimoto

Cu/photosensitive-BCB thin-film multilayer technology for high-performance multichip modules

A new MCM-D technology which enables reliable fabrication of high-performance and low cost MCMs has been developed. The technology is based on Cu/photosensitive-BCB thin-film multilayer structure. The fabrication process is reduced by using the newly developed photosensitive-BCB, with a conventional photolithography process. The flexibility on design rules is allowed, because the Cu/BCB structure has the advantages of excellent planarization and low electrical resistance of signal line. The following long-term reliability tests were successfully done: thermal cycle (-45/spl deg/C/125/spl deg/C), high-temperature aging at 125/spl deg/C, and high-temperature/humidity (85/spl deg/C/85%). A prototype of the high density RISC module fabricated with the developed technology passed all the long-term reliability tests. The excellent electrical performance was also proved through the signal transmission tests with the prototype module. >

New high-density multilayer technology on PCB

Demand has recently increased for very high-density packaging substrates for high-pin-count area array chips. Our new high-density multilayer technology on printed circuit board (PCB), named deposited substrate on laminate (DSOL) satisfies this demand. An important feature of the DSOL is dielectric fabrication, which uses a new photosensitive material; an aromatic fluorene unit bonded epoxy acrylate resin. The fluorene based resin has interesting properties such as good electrical properties, low curing temperature (160/spl deg/C) for a heat-resistant resin (glass transition temperature, T/sub g/=230/spl deg/C), low coefficient of the thermal expansion (40 ppm), and excellent via hole resolution. Very fine and high-aspect-ratio (>1.0) via holes were formed through exactly the same process steps as those used for a conventional photosensitive epoxy resin; baking, exposure, and development with an aqueous alkaline solution. Another important feature is the technology, that patterns fine-pitch Cu conductors using a semi-additive process with a sputtering method. The DSOL made 40 /spl mu/M very fine pitch Cu conductors on large laminates (330 mm/spl times/400 mm) possible, because this process was composed of flash wet etching of only 0.3 /spl mu/m thick sputtered thin-films. We have successfully developed a high-density packaging substrate for high-pin-count (4000 pins) area array application specific integrated circuit (ASIC) chips.

Cu/Photosensitive-BCB Thin-Film Multilayer Technology for High-Performance Multichip Module

A new MCM-D technology which enables reliable fabrication of high-performance and low cost MCMs has been developed. The technology is based on Cu/Photosensitive-BCB thin-film multilayer structure. The fabrication process is reduced by using the newly developed Photosensitive-BCB, with a conventional photolythography process. The flexibility on design rules is allowed, because the Cu/BCB structure has the advantages of excellent planarization, and low electrical resistance of signal line. Long-term reliability test was successfully done; thermal cycle(-45/spl deg/C/125/spl deg/), high-temperature aging at 125/spl deg/C, and high-temperature/humidity(85/spl deg/C/85%). A prototype of high-density RISC module fabricated with the developed technology passed all the long-term reliability tests. The excellent electrical performance was also proved through the signal transmission tests with the prototype module.

High-performance FCBGA based on multi-layer thin-substrate packaging technology

Abstract We developed a new concept flip-chip ball grid array (FCBGA) based on multi-layer thin-substrate (MLTS) packaging technology in order to meet the strong demand for high-density, high-performance, and low-cost LSI packages. The most important feature of MLTS packaging is that, only a high-density and high-performance MLTS remains by removing the metal plate after mounting an LSI chip. The MLTS packaging offers the advantages of (1) good registration accuracy, which makes higher-density and finer-pitch pattering possible; (2) an ideal multi-layer structure that is highly suitable for high-speed and high-frequency applications; (3) excellent flip-chip mounting reliability, which makes higher-pin-count and finer-pitch area array flip-chip interconnection possible; (4) excellent reliability, supported by use of high T g (glass transition temperature) resin; and (5) a cost-effective design achieved as a result of fewer layers fabricated with fine-pitch patterning. We successfully produced a high-performance FCBGA prototype based on our MLTS packaging technology. The prototype comprises an LSI chip connected to approximately 2500 bonding pads arranged in 240 μm pitch area array, and 1296 I/O pads for BGA. The prototype FCBGA’s excellent long-term reliability was demonstrated through a series of tests conducted on it.

New MCM composed of D/L base substrate, high-density-wiring CSP and 3D memory modules

A RISC (reduced instruction set computer) module, which contains secondary cache memories and is called an MCM for use in a high-performance workstation has been developed. The design consists of a D/L (deposited organic thin film on laminated printed-circuit board) base substrate, a glass-ceramic-based organic-thin-film multilayer build-up CSP (chip size package), and glass-ceramic 3-dimensional memory (3DM) modules. The characteristics of this newly developed MCM are as follows. The D/L base substrate has 179 I/O (input/output) pins and signal lines of 25-/spl mu/m width and 50-/spl mu/m pitch. The CSP carrier signal lines are as fine as those of the D/L, and the CSP carrier features 525 I/O pads and 80-/spl mu/m diameter chip bonding pads with 108-/spl mu/m pitch. The 3DM is almost the same size as a conventional single chip mold package; with the stacking of ten memory chips in the space of four 3DMs, the area required is roughly only that of four single chip packages.

Ultra-Thin High-Density LSI Packaging Substrate for Advanced CSPs and SiPs

Abstract An ultra-thin high-density LSI packaging substrate, called multi-layer thin substrate (MLTS), is described. It meets the demand for chip scale packages (CSPs) and systems in a package (SiPs) for use in recently developed small portable applications with multiple functions. A high-density build-up structure is fabricated on a Cu plate, which is then removed, leaving only an ultra-thin, high-density multi-layer substrate. MLTS has (1) excellent registration accuracy, which enables higher density and finer pitch patterning due to the use of a rigid, excellent-flatness Cu base plate; (2) a thinner multi-layer structure due to the use of a core-less multi-layer structure; (3) excellent reliability, supported by the use of an aramid-reinforced epoxy resin dielectric layer; and (4) a cost-effective design due to the use of fewer layers fabricated using a conventional build-up process. A prototype high-density CSP (0.4-mm pitch/288 pins/4 rows/10 mm2) was fabricated using a 90-μm-thick MLTS (with a solder resist layer). Testing demonstrated that it had excellent long-term reliability. A prototype ultra-thin, high-density SiP (0.5-mm pitch/225 pins/11 mm2/0.93 mm thick) was also fabricated based on MLTS. MLTS consists of only two conductor layers (total thickness: 90 μm) while an identical-function build-up printed wiring board needs four conductor layers (total thickness: 300 μm). With its thinner core-less multi-layer structure, MLTS enables the fabrication of ultra-thin, high-density SiPs.

A silicon-on-silicon packaging technology for advanced ULSI chips

A RISC (reduced instruction set computer) module for high-performance workstations has been made to demonstrate the advantages and technical feasibility of the silicon-on-silicon technology. The module consists of one 0.8-/spl mu/m CMOS CPU (central processing unit) one 0.8-/spl mu/m CMOS FPU, and six 1.0-/spl mu/m BiCMOS cache memories. The eight chips are attached on a 39/spl times/47 mm square silicon substrate with 120-/spl mu/m pitch flip chip bonding of 80-/spl mu/m-diameter tin-lead bumps. Two-layer interconnections for high-speed signals are formed with 20-/spl mu/m line and 80-/spl mu/m space on the silicon substrate. The conductors are 4-/spl mu/m thick gold formed by electroplating and the dielectric film is 10-/spl mu/m-thick polyimide. A decoupling capacitance of about 0.8 nF is formed in the substrate. The module was evaluated using reliability and functional tests. The reliability tests included thermal cycling, power cycling, and mechanical strength tests. The functional test was carried out by connecting the module to an IBM-PC/IF board and operating with a test program. Both evaluations were successful.<<ETX>>

The ferrite-embedded drop-in circulator for millimeter wave communication systems

We have developed a ferrite-embedded drop-in circulator (FEC) that operates on the W-band for millimeter wave communication systems. The FEC is taken as the composite structure, that is, the Sr-ferrite disc is embedded in a dielectric layer which is formed on an alumina substrate. The FEC does not require a magnet by using the large anisotropy field, H/sub a/ of Sr-ferrite. And the FEC has a high flexural strength and has a coefficient of thermal expansion (CTE) similar to that of ceramic materials which are used for a multi-chip radio frequency (RF) module. As a result, the FEC can be assembled directly on multi-chip RF module. Moreover, benzocyclobutene (BCB), an organic resin, is the material used in the dielectric layer of the FEC. Using organic resins like BCB in the dielectric layer makes the process of embedding ferrite easy and simplifies fabrication. BCB also offers other advantages such as low dielectric loss, low moisture absorption, and excellent planarization. The optimumly configured FEC performed well, demonstrating an insertion loss of less than 2 dB, a return loss of more than 20 dB, and an isolation of more than 25 dB at 60 GHz. Using the MCM with the FEC directly assembled. Millimeter wave communications equipment are expected to have less than a tenth volume of conventional equipment and also to decrease in cost.