Naoki Tega

Anomalously Large Threshold Voltage Fluctuation by Complex Random Telegraph Signal in Floating Gate Flash Memory

A threshold voltage fluctuation (DeltaVth) due to random telegraph signal (RTS) in a floating-gate (FG) flash memory was investigated. From statistical analysis of the DeltaVth, we found an anomalously large DeltaVth at high percentage region of the DeltaVth distribution, which is caused by a complex RTS. Since the ratio of the complex RTS among the RTS is increased by charge injection to tunnel oxide, the dispersion of the DeltaVth distribution increases after program/erase (P/E) cycle. Since the DeltaVth due to the complex RTS is much larger than the simple RTS, the complex RTS become one of the reliability issues in larger capacity flash memory, especially after P/E cycle

Impact of threshold voltage fluctuation due to random telegraph noise on scaled-down SRAM

The impact of a random telegraph noise (RTN) on a scaled-down SRAM is shown for the first time. To estimate the impact on SRAM, we statistically analyzed a threshold voltage fluctuation (DeltaVth) of n-and p-MOSFETs. It is revealed that DeltaVth of the p-MOSFET is larger than that of the n-MOSFET. This difference can be explained by considering the followings: (i) number- and mobility-fluctuation models of RTN (ii) the difference in the capture cross section between electron and hole. In addition, based on these results, SRAM margin enclosed by read / write Vth curves with or without RTN was simulated. We consequently found that Vth margin comes close to Vth window of the SRAM by considering the effect of RTN on DeltaVth, even at hp 65. Moreover, DeltaVth due to RTN of the p-MOSFET is comparable with DeltaVth due to the random dopant fluctuation (RDF) at hp 45 because DeltaVth due to the RDF is inversely proportional to square root of the gate area (S), while DeltaVth due to RTN is inversely proportional to S.

Statistical measurement of random telegraph noise and its impact in scaled-down high-κ/metal-gate MOSFETs

This paper presents results of statistical analysis of RTN in highly scaled HKMG FETs. A robust algorithm to extract multiple-trap RTN is proposed and applied to show that RTN can cause serious variation even when HKMG and undoped channel are introduced. We further focus on hysteretic behavior caused by RTN with time constants much longer than the circuit timescale. This reveals that RTN also induces novel instabilities such as short-term BTI and logic delay uncertainty. Extraction of RTN in SRAM arrays is also presented to discuss its impact on operational stability.

Reduction of random telegraph noise in High-к / metal-gate stacks for 22 nm generation FETs

This work demonstrates, for the first time, the reduction of random telegraph noise (RTN) in high-к / metal gate (HK / MG) stacks incorporated in 22 nm generation FETs. Many thousands of such FETs have been fabricated, measured, and analyzed using a statistical technique to separate RTN as a major noise component from 1/f noise as a minor component. Based on a statistical comparison of these FETs, we find that high temperature forming gas annealing can suppress RTN threshold voltage variation (ΔVth). In addition, properly annealed HK FETs have smaller RTN ΔVth than SiON FETs, due mostly to fewer traps and partly to thinner inversion thickness in HK / MG. Based on these results, we project that random dopant fluctuations will have a greater impact on SRAM yield than RTN until at least the 15 nm generation, for doped channel FETs.

Quantitative Analysis of Random Telegraph Signals as Fluctuations of Threshold Voltages in Scaled Flash Memory Cells

Random telegraph signals (RTS) in fluctuations of threshold voltage are analyzed using massive readout data in scaled flash memories. A novel quantitative analytical method is proposed to evaluate parameters of the RTS, such as amplitudes and mean time spent in individual states. This evaluation gives us a statistical view of parameters of the RTS as well as their correlations. All of the parameters were found to follow log-normal distribution and to show weak mutual dependences. Possible origins of the distributions are discussed. We also studied evolution of RTS during program/erase operations of flash memories and point out its potential similarity with breakdown phenomena in gate oxide

Impact of HK / MG stacks and future device scaling on RTN

This work demonstrates the close relationship between device scaling and the threshold voltage variation (ΔVth) of random telegraph noise (RTN) in high-κ and metal gate (HK / MG) stacks. Statistical analysis clarifies that high temperature forming gas annealing can suppress the RTN ΔVth. And properly annealed HK FETs have smaller RTN ΔVth than SiON FETs, due mostly to fewer traps and partly to thinner inversion thickness in HK / MG stacks. Consequently, the influence of RTN on HK / MG gate stacks is less than that of random dopant fluctuation in the 22 nm generation. However, RTN may pose a difficult challenge for the 15 nm generation. In addition to the scaling dependence, we also find that characterizing hysteretic RTN behaviors due to RTN dependence on bias is essential to determine whether the observed RTN has an impact on SRAM operation or not.

Hysteretic drain-current behavior due to random telegraph noise in Scaled-down FETs with high-κ/metal-gate stacks

This work demonstrates for the first time that hysteretic effects associated with random telegraph noise (RTN) can lead to the short-term enhancement of drain current in the turn-on transient of scaled-down FETs. Comprehensive time domain analyses of this hysteretic behavior prove that it is a consequence of the voltage-dependence of the capture and emission rates of the RTN traps, which is measured deep into the subthreshold regime using a new technique. Relevant trap parameters are proposed and statistically accumulated. Understanding and characterizing this temporal behavior is essential to determining the impact of RTN on scaled SRAM operation.

A new insight into the dynamic fluctuation mechanism of stress-induced leakage current

The dynamic fluctuation of stress-induced leakage current, called V-SILC, which is one of the causes of erratic bits in flash memory, was investigated. The effect of V-SILC on flash memory retention increases with the scaling down of device dimensions because the amplitude of V-SILC is constant and does not depend on the gate area. A statistical analysis of V-SILC indicated that V-SILC is random telegraph noise (RTN) of gate SILC and is associated with the state transition of a single defect in a gate oxide. The state transition of the defect is caused by an electron collision with the defect.

Effects of interface properties in SiC MOSFETs on reliability

Based on the experience with silicon (Si) devices, some characteristics of silicon carbide (SiC) devices are likely to be misunderstood. In this paper, studies on channel mobility, time dependent dielectric breakdown (TDDB), and negative bias temperature instability (NBTI) in 4H-SiC MOSFETs are reviewed. Through the discussions, it is indicated that SiC-based models, such as local band gap modulation, and models for the relationship between defect energy state and SiC band gap are effective to understand the above characteristics.

Two-component model for long-term prediction of threshold voltage shifts in SiC MOSFETs under negative bias stress

The negative bias temperature instability in SiC MOSFETs was investigated. Considering the time, temperature, and bias dependences of the threshold-voltage (Vth) shift, we propose a two-component model for long-term prediction. On the basis of fitting results, we discuss the origins of these components. The first component, which dominates short-term instability, was found to show reverse temperature and weak bias dependences. Such trends are consistent with the carrier exchange of pre-existing slow oxide traps, which are O vacancies. After subtracting the first component, the second component was found to show power-law time dependence, similar to that observed in Si devices. The forward temperature and strong bias dependences of the second component indicate the activation of additional traps. The activation energy of 0.1 eV is consistent with that of a Si device using nitrided gate oxide. Therefore, the origin of the long-term Vth shift of SiC-MOSFETs was suggested to be a nitrogen-related site. Control of the amount of nitrogen is expected to be important for the long-term threshold stability of SiC-MOSFETs.