Aki Dote

Thermal stress reliability of copper through silicon via interconnects for 3D logic devices

For 3D-LSI devices using the through silicon via (TSV) process, there are many reliability issues regarding the large thermal-mechanical stress and deformation volume changes caused by mismatch of the thermal expansion coefficients (CTEs) between the Cu and Si substrate in the device active area. In this paper, we investigated the TSV leakage current in metal-insulator-semiconductors and studies MOSFET device characteristics to manage manufacturing quality based on stress propagation of Cu-TSVs by thermal loading in the operating temperature range (−50 to 80 °C) and relatively high process temperature range (250 to 400 °C). The stress induced leakage current and MOSFET mobility change showed a relationship between expansion and contraction deformation of Cu under the thermal loading conditions. These results show that Cu/Si interface formation quality is high although there is major TSV metallization. Furthermore, it was found that precise estimation is important to designing the keep out zone (KOZ) in consideration of the real operating temperature.

Analyzing and modeling methods for warpages of thin and large dies with redistribution layer

Analyzing and modeling methods for warpages including cylindrical deformations are discussed in large-area dies with redistribution layers (RDLs) and thin 50-µm-thick Si substrates. The buckling behavior of warpage, a deformation transition from spherical to cylindrical, strongly depends on the lateral sizes of the dies and the RDL structures, and can be calculated using the analytical model of the nonlinear plate theory. The equivalent stress values are introduced to simplify RDL structures by applying the model to measured curvatures of homogeneous patterned samples. Area densities of Cu are a good index for evaluating die warpage even for inhomogeneous patterned RDLs.

Study of MOSFET thermal stability with TSV in operation temperature using novel 3D-LSI stress analysis

A large thermal-mechanical stress caused by the mismatch of thermal expansion coefficients (CTEs) between the copper and silicon substrate occurs in the active area of the stacked 3D device using the through-silicon via (TSV). Therefore, the study of TSV-induced stress is of fundamental importance in our understanding of the keep-out zone (KOZ). We investigated the metal-oxide-semiconductor field-effect transistor (MOSFET) thermal stability of a device operated by combining Technology Computer-Aided Design — Simulation Program with Integrated Circuit Emphasis (TCAD-SPICE) stress analysis and an actual ring oscillator circuit (ROSC) nearby TSVs. The MOSFET drain current (Id) fluctuates in response to the behavior of the Si stress caused by the TSVs. However, it was found that the simulation and test measurement results showed that the KOZ becomes smaller because the electric charge/discharge is canceled in the case of a p/n MOS inverter circuit. This study showed the importance of the design of the KOZ, which includes the temperature fluctuation phenomenon in a real integrated circuit device operation.

Characterization of Warpages and Layout-Dependent Local-Deformations for Large Die 3D Stacking

Modeling and controlling of warpages and layout-dependent local-deformations are challenges to overcome to realize 3D stacking of dies with through-silicon vias and micro-bumps. Dies larger than about 500 mm2 are now being used for high performance computing, and large cylindrical warpage of the die and local die surface deformations can greatly affect the yield and reliability of the stacked dies. We have analyzed and modeled large cylindrical warpage with layout-dependent local-deformations by using a combination of an analytical buckling model, curvature measurements of dies with simple layout patterns, and finite element analysis (FEA) simulation. The effects of warpage on the buckling behavior were roughly estimated by using an analytical model based on non-linear plate theory and were precisely calculated using FEA simulation. The model was applied to actual dies by measuring the curvature of simple structures and by homogenizing complicated device structures into simple elastic films. Finally, die warpage with layout-dependent local deformations was modeled using a patchwork of elastic film on a Si substrate. This approach was tested on dies with a redistribution layer (RDL) structure and a 50-μm-thick Si substrate. The simplified FEA simulation results and experimentally measured deformations matched well. The RDL consisted of elastic materials (polymer) and plastic materials (metal interconnections) so this method can be applied to other structures such as multilayer interconnects with LSI or bump structures. It can be used to calculate the deformation of a large die during the design phase, which will enable die warpage and local deformations to be managed by optimizing the device layout. This will improve yield and reliability in 3D fabrication.