Natsuro Tsubouchi

CAD-compatible high-speed CMOS/SIMOX gate array using field-shield isolation

A specific 0.5 /spl mu/m CMOS/SIMOX technology was developed for a gate array/sea of gate (SOG) using field-shield (FS) isolation to overcome a pending problem of source-to-drain breakdown voltage (BV/sub ds/) lowering. FS isolation is capable of improving BV/sub ds/ because surplus holes generated by impact ionization at the drain region are collected through the body region under the FS gate. BV/sub ds/ was maintained at a level of junction breakdown before reaching the punchthrough limitation at a gate length of around 0.3 /spl mu/m using the FS isolation. The FS isolation technique was successfully applied to an SOG gate array on a SIMOX substrate. The gate array has the same area as that on the bulk-Si and is compatible to a conventional bulk-Si CAD system because the layout is basically the same. A 53-stage ring oscillator fabricated on the FS isolated SOG gate array exhibited 1.7 times higher speed operation than that on a bulk-Si counterpart, keeping low power consumption characteristics up to a drain voltage of 3 V. >

0.15 /spl mu/m CMOS process for high performance and high reliability

We have developed a novel 0.15 /spl mu/m CMOS process for high performance and high reliability, consisting of mixing the CoSi/sub 2/-Si interface using Si/sup +/ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using these processes, the propagation delay time of 21 psec/stage was obtained for a 0.15 /spl mu/m CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.<<ETX>>

CAD-compatible high-speed CMOS/SIMOX technology using field-shield isolation for 1 M gate array

A specific 0.5 /spl mu/m CMOS/SIMOX technology was developed for a 1 M gate array/SOG (Sea Of Gates) using field-shield (FS) isolation to overcome a pending problem of source-to-drain breakdown voltage (BV ds) lowering. The ring oscillator fabricated on the FS isolated SOG gate array exhibited 1.7 times higher speed operation than that on a bulk-Si counterpart keeping the lower power consumption feature even at a relatively high drain voltage of 3 V.<<ETX>>

A 1" format 1.5 M pixel IT-CCD image sensor for an HDTV camera system

A 1-in. format 1.5-million pixel IT (interline transfer) CCD (charge coupled device) image sensor has been developed for an HDTV (high-definition television) camera system. To achieve a low smear ratio while maintaining a high level of sensitivity, the authors have developed a new impurity profile of a buried P/sup +/-layer and an on chip microlens array whose material is a deep-UV resist. Using this sensor, a high-fidelity picture with a horizontal resolution of 820 TV lines has been obtained. The IT-CCD sensor has achieved a smear ratio of less than -90 dB, a sensitivity level of 80 nA/Lx, and a maximum charge handling capacity of 1.2*10/sup 5/ electrons. >

A PtSi Schottky-barrier infrared MOS area imager with large fill factor

A 64 × 64-element silicon monolithic infrared MOS area imager (IR-MOS) with platinum silicide Schottky barrier (PtSi S.B.) detectors has been developed. Using MOS X-Y address circuitry, the fill facter of the device increased to 56 percent without degradation of the dynamic range. The dynamic range was 48 dB The responsivity was2.9\times10^{8}V/W at 1000 K and the sensitivity was 10.5 mV/K at 300 K. The performance of the IR-MOS was sufficient to obtain a thermal image in the range of the 3 to 5 µm atmospheric window without any electrical compensation of the imaged signal.

Improved 512 x 512 IRCSD with large fill factor and high-saturation level

We have improved the performance of a 512 X 512 element PtSi Schottky-barrier infrared image sensor (512 X 512 IRCSD) by increasing the fill factor and saturation signal level. The sensor consists of 26 micrometers X 20 micrometers pixels in a 512 X 512 array format and has a large fill factor of 71% obtained with 1.2 micrometers minimum design rules and the charge sweep device (CSD) readout architecture. The improved 512 X 512 IRCSD was designed to be operated in either a field or frame integration interlace mode. The saturation signal level of the CSD imager is determined by the storage capacity of the Schottky-barrier detector (SBD). We optimized the structure and impurity concentration of the isolation region of the SBD in order to increase the large storage capacity. For an SBD reset voltage of 4 V, a saturation signal level and differential temperature response at 300 K were 2.9 X 106 electrons and 3.2 X 104 electrons/K, respectively. The noise equivalent temperature difference (NETD) at 300 K is estimated as 0.033 K with an f/1.2 cold shield.

A simulation of plastic deformation of silicon during thermal oxidation

Plastic deformation of silicon during thermal oxidation has been simulated using the finite element method. The von Mises yield criterion is assumed for the plastic deformation of silicon. In order to solve a pure elasto-plastic problem, an elasto-visco-plastic algorithm is used with stationary conditions. As an application example, local oxidation of silicon has been simulated, and the result demonstrates that plastic deformation is initiated at the edge of the nitride mask, and expands into substrate silicon as oxidation proceeds.<<ETX>>

Selection of operation mode on SOI/MOSFETs for high-resistivity load static memory cell

SOI/MOSFETs are widely known to have some advantages such as reduction of parasitic capacitance, improvement of subthreshold characteristics and increased drive current, compared with bulk-Si/MOSFETs. Moreover, this structure provides the reduction in the substrate-bias effect because the back-gate bias (Si substrate) is applied to the channel region through thick buried oxide. In the present paper, we propose the best choice of operation mode of SOI/MOSFETs in a high-resistivity load SRAM cell to improve the stability in the memory cell and to obtain sufficient static noise margin providing non-destructive reading of cell data at low supply voltage.<<ETX>>