Hannah Honghua Yang

Integrating dynamic thermal via planning with 3D floorplanning algorithm

Incorporating thermal vias into 3D ICs is a promising way to reduce circuit temperature by lowering down the thermal resistances between device layers. In this paper, we integrate dynamic thermal via planning into 3D floorplanning process. Our 3D floorplanning and thermal via planning approaches are implemented in a two-stage approach. Before floorplanning, the temperature-constrained vertical thermal via planning is formulated as a convex programming problem. Based on the analytical solution, blocks are assigned into different layers by solving a sequence of knapsack problems. Then a SA engine is used to generate floorplans of all these layers simultaneously. During floorplanning, thermal vias are distributed horizontally in each layer with white space redistribution to optimize thermal via insertion. Experimental results show that compared to a recent published result from [14], our method can reduce thermal vias by 15% with 38% runtime overhead.

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization

Three-dimensional (3-D) IC physical design problems are usually of higher complexity, with a greatly enlarged solution space due to multiple device structure. In this paper, a new 3-D floorplanning algorithm is proposed for wirelength optimization. Our main contributions and results can be summarized as follows. First, a new hierarchical flow of 3-D floorplanning with a new inter-layer partitioning method. The blocks are partitioned into different layers before floorplanning. A simulated annealing (SA) engine is used to partition blocks with the objective of minimizing the statistical wirelength estimation results. The solution quality is not degraded by the hierarchical flow. Second, floorplans of all the layers are generated in a SA process. Original 3-D floorplanning problem is transformed into solving several 2-D floorplanning problems simultaneously. The solution space is scaled down to maintain a low design complexity. Finally, Experimental results show that our algorithm improves wirelength by 14%-51% compared with previous 3-D floorplanning algorithms. The hierarchical approach is proven to be very efficient and offers a potential way for high-performance 3-D design

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration

New three-dimensional (3D) floorplanning and thermal via planning algorithms are proposed for thermal optimization in two-stacked die integration. Our contributions include (1) a two-stage design flow for 3D floorplanning, which scales down the enlarged solution space due to multidevice layer structure; (2) an efficient thermal-driven 3D floorplanning algorithm with power distribution constraints; (3) a thermal via planning algorithm considering congestion minimization. Experiments results show that our approach is nine times faster with better solution quality compared to a recent published result. In addition, the thermal via planning approach is proven to be very efficient to eliminate localized hot spots directly.

3D placement algorithm considering vertical channels and guided by 2D placement solution

3D integration is a potential solution to solve complex problem caused by interconnect delay that dominates the total budgets. In this placer, we bring up a 3D placement algorithm and focus on two issues: the effect of vertical channels and the constraint that cells can not leave the plane after assigned to it. Firstly, we develop an algorithm to verify the effect of vertical channels in wire length optimization. Secondly, because of the constraint presented above the placement quality is restricted badly. We research the possibility of improving placement quality by importing an initial solution. Experiments on a set of benchmarks prove our algorithm efficient and effective.

An effective floorplanning algorithm in mixed mode placement integrated with rectilinear-shaped optimization for soft blocks

Mixed mode placement (MMP) problem can be successfully solved by combining floorplanning and cell based placement according to circuits hierarchy. Floorplanning is the key design stage for achieving optimum performance if virtual blocks (VB: Soft Block) in floorplanning are not restricted to only have rectangular shapes. In this paper, an effective floorplanning algorithm RSF used in MMP is presented to perform the rectilinear-shaped optimization for VBs. Our approach allows VBs to transform into rectilinear shapes without overlaps and selects the optimum shapes for them during topology optimization of normal floorplanning. It is based on the dead-space block assignment and pin allocation during the process of packing. It depends on the theoretic analysis on lower bound of net wire length in half perimeter mode which makes RSF result in shorter total wire length in floorplanning. Applied in MMP, RSF can improve the final performance of MMP.

Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration

Mixed mode placement (MMP) is characterized by a number of same-height standard cells mixed with scattering big blocks in a fixed die. The variety of size and number of blocks introduces challenges to existing algorithms in achieving reasonable solution quality and running time. A new design flow named recursive mixed mode placement (RMMP) is presented in this paper to provide a solution of MMP with this circuits variety of block configuration taken into account. It starts from recursively partitioning circuits to form a tree of virtual blocks in the different condition of the size and number of blocks as well as the logical or physical hierarchy. Then it combines floorplan on block level and quadratic place (Q-place) on cell level to complete the global placement. Our approach takes advantage of combining floorplan and Q-place algorithms to fit the variety of circuits components. The combined approach improves the algorithm efficiency and obtains satisfactory results of MMP in terms of wire length and running time on various industry and academia test cases.

Design tools for 3D mixed mode placement

We present a set of design tools for three dimensional (3D) mixed mode placement (MMP). The hierarchical 3D MMP design tool is composed of a hierarchical clustering package, a new 3D floorplanning tool, route planning tool, and 2D global/detailed placement tools. We have analyzed the performance of 3D circuit using these tools. It is shown that total wirelength could be reduced by 25% to 43% compared with traditional 2D design using two to four stacked dies. By incorporating thermal management and analysis, we also investigate the thermal scalability of 3D integration

A fast and stable force-directed placement with implicit buffer planning

As technology advances, the number of required buffers increases significantly and it is desirable to plan buffers at placement stage. This paper studies the approach of planning buffers during analytical placement. First, a fast and stable force-directed placement is introduced, which is averagely 1.71 times as fast as Capo8.8, a state-of-the-art placement tool, with little degradation of wire-length. Then a new model for planning buffers during placement is proposed, which can efficiently ensure the convergence of placement iterations only by modeling buffers implicitly with changed density distribution and modified connectivity weight between drivers and receivers. Also, equivalent candidate positions for buffer insertion are explored to resolve buffer overlaps. Experiments show that compared with previous buffer planning methods, our new approach can achieve greater efficiency as well as quality improvement