Nebojsa Jankovic

A model for capacitance reconstruction from measured lossy MOS capacitance-voltage characteristics

A capacitance model is developed and a correction formula is derived to reconstruct the intrinsic oxide capacitance value from measured capacitance and conductance of lossy MOS devices. Due to discrepancies during processing, such as cleaning, an unwanted lossy dielectric layer is present in the oxide/semiconductor interface causing the measured capacitance in strong accumulation to be frequency dependent. The capacitance–voltage characteristics after correction are free from any frequency dispersion effect and give the actual oxide thickness in accumulation at all frequencies. Simulation of the measured capacitance–frequency curve was carried out using the model. The model was applied to SiO2/Si, SiO2/strained Si and GaO2/GaAs MOS capacitors.

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

Abstract A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N + polysilicon gate device with highly doped Si layer, an asymmetrical P + /N + polysilicon gate device with low doped Si layer and a mid-gap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P + /N + polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET.

Unified Approach in Electro-Thermal Modelling of IGBTs and Power PiN Diodes

The unified electro-thermal modelling of the IGBT and power PiN diode based on modified minority carrier drift- diffusion (DD) theory is described in this paper. PiN and IGBT models are embedded in PSPICE commercial simulation software and successfully tested against commercially available power devices.

Enhanced performance virtual substrate heterojunction bipolar transistor using strained-Si/SiGe emitter

We have investigated the influence of strained-Si cap layers on n–p–n heterojunction bipolar transistors (HBTs) fabricated on virtual substrates. Using an approximate theoretical model, it is found that the presence of a strained-Si/SiGe (relaxed) heterojunction barrier in the emitter can substantially improve the HBTs current gain, relaxing the need for a high Ge content in the strained base. Furthermore, two-dimensional numerical simulations of a virtual substrate HBT with a realistic geometry demonstrate that, besides the current gain enhancement, a three times improvement in ft and fmax can be realized when a strained-Si/SiGe emitter is incorporated.

An analytical model of the inverse base width modulation effect in SiGe graded heterojunction bipolar transistors

Abstract The analytical model of the collector current ideality factor degradation at high V be in modern SiGe graded base heterojunction bipolar transistors (HBTs) has been developed for the first time. It is subsequently used for the analysis of the inverse base width modulation (IBWM) effects in SiGe HBTs with respect to collector current degradation, current gain premature roll-off and SiGe base transit time. Comparing the IBWM effects calculated for HBTs with various base impurity concentration doping profiles and the Ge grading, we have found that the careful optimization of SiGe base parameters may substantially minimize negative influence of the IBMW effects on the HBT electrical parameters.

A lateral double-diffused magnetic sensitive metal-oxide-semiconductor field-effect transistor with integrated n-type Hall plate

A magnetic sensitive device, lateral double-diffused magnetic sensitive metal-oxide-semiconductor field-effect transistor (LD MagFET), combining the sensory operation of conventional magnetic sensitive metal-oxide-semiconductor field-effect transistors (MagFETs) and Hall plates is proposed. The sensor device is fully compatible with a high-voltage complementary metal-oxide-semiconductor (CMOS) technology. It is found that the LD MagFET with integrated Hall plate exhibits an order of magnitude higher relative magnetic sensitivity in comparison with the split-drain silicon MagFETs in standard CMOS.

A compact nonquasi-static MOSFET model based on the equivalent nonlinear transmission line

A compact physics-based nonquasi-static (NQS) metal-oxide-semiconductor field-effect transistor (MOSFET) model with the equivalent nonlinear transmission line (TL) representing channel carriers drift-diffusion transport is developed and implemented in the simulation program with integrated circuit emphasis (SPICE) program. An auxiliary subcircuit is described, which efficiently solves the channel surface boundary potentials without the need for employing separate iterative algorithms. The short-channel effects and the quantum effects are efficiently included owning to a surface-potential-based modeling approach. In comparison with other Berkeley short-channel IGFET model 3 (BSIM3)-based NQS MOSFET models, it is shown that the new NQS TL model has the advantages in higher accuracy and substantially fewer number of model parameters. From comparison with a two-dimensional device simulator, it is demonstrated that the new NQS TL model can accurately predict dc, ac, and transient behavior of long- and short-channel n-type MOSFETs in all operational regions and for the input signal frequencies up to 10 f/sub T/ values, using only one set of model parameters.

Experimental Evaluation of Circuit-Based Modeling of the NBTI Effects in Double-Gate FinFETs

Abstract In this work, an example of practical implementation of the auxiliary sub-circuit (ASC) for modeling of the NBTI effects in DG FinFETs is described. A good agreement between the simulated and measured electrical characteristics of p-type DG FinFETs fabricated in SOI technology has been obtained using the industry-standard BSIM-CMG model with ASC. The oxide and interface trap densities are extracted in Spice simulations by tuning the ASC trapped charge parameters to fit the NBTI experimental data. The increase of oxide and interface trapped charge in p-type DG FinFET device is found to follow the logarithmic dependence with NBTI stress time.

Numerical simulations of N-type CdSe poly-TFT electrical characteristics with trap density models of Atlas/Silvaco

Abstract In this work, the two-dimensional numerical simulations of N -type CdSe polycrystalline (poly-) TFTs’ electrical characteristics are performed using a physically based device simulator Atlas/Silvaco. The analytical expressions of trap density models for acceptor- and donor-like traps are defined for poly-CdSe thin film material. The parameters of trap density distributions are extracted based on fitting the simulated and measured results of fabricated CdSe poly-TFTs. It is shown that the discrete numerical method used for trapped charge evaluation in Atlas gives excellent agreement between simulated and measured characteristics, while the continuous numerical approach is less accurate. In addition, the interface trapped charge causing hysteresis in device transfer characteristics is estimated from simulations and shown to increase almost exponentially with the increase of density of shallow tail states.

An advanced physics-based sub-circuit model of a punch-trough insulated gate bipolar transistor

An advanced sub-circuit model of the punch-trough insulated gate bipolar transistor (PT IGBT) based on the physics of internal device operation has been described in this article. The one-dimensional physical model of low-gain wide-base BJT is employed based on the equivalent non-linear lossy transmission line, whereas a SPICE Level 3 model is used for the diffused MOST part. The influence of voltage dependent drain-to-gate overlapping capacitance and the conductivity modulated base (drain) ohmic resistance are modelled separately. The main advantages of novel PT IGBT model are a small set of model parameters, an easy implementation in SPICE simulator and the high accuracy confirmed by comparing the simulation results with the electrical measurements of test power circuit.