Nebojša Stanić

A 2.4-GHz ISM-Band Sliding-IF Receiver With a 0.5-V Supply

We report an ultra-low-voltage RF receiver for applications in the 2.4 GHz band, designed in a 90 nm CMOS technology. The sliding-IF receiver prototype includes an LNA, an image-reject LC filter with single-ended to differential conversion, an RF mixer, an LC IF filter, a quadrature IF mixer, RF and IF LO buffers, and an I/Q baseband section with a VGA and a low-pass channel-select filter in each path, all integrated on-chip. It has a programmable overall gain of 30 dB, noise figure of 18 dB, out-of-channel IIP3 of -22 dBm. The 3.4 mm2 chip consumes 8.5 mW from a 0.5 V supply.

A 0.5 V 900 MHz CMOS Receiver Front End

A 900 MHz RF receiver front end including an LNA, downconversion mixer and associated LO buffers is presented. All circuits operate from a 0.5 V supply without any internal voltage boosting. The circuit is designed in 0.18 mum standard CMOS. It achieves a conversion gain of 12 dB, an IIP3 of -14 dBm and a noise figure of 9 dB. The circuit, including the LO buffers, dissipates 7.4 mW and occupies an active area of 0.43 mm2

A 0.5 V Receiver in 90 nm CMOS for 2.4 GHz Applications

We report an ultra-low voltage RF receiver for applications in the 2.4 GHz band, designed in a 90 nm CMOS technology. The sliding-IF receiver prototype includes an LNA, an image-reject LC filter with single-ended to differential conversion, an RF mixer, an LC IF filter, a quadrature IF mixer, RF and IF LO buffers, and an I/Q baseband section with a VGA and a low-pass channel-select filter in each path, all integrated on-chip. It has a programmable overall gain of 30 dB, noise figure of 18 dB, out-of-channel IIP3 of -22 dBm, and 26 dB of on-chip image rejection. The 3.4 mm2 chip consumes 8.5 mW from a 0.5 V supply.

An integrated 1.5 V 6 GHz Q-enhanced LC CMOS filter with automatic quality factor tuning using conductance reference

We report the design of an integrated 4/sup th/-order Q-enhanced LC bandpass filter with automatic Q tuning. The filter passband is centered at 6 GHz, and has a bandwidth of 100 MHz. The filter draws 15 mA from a 1.5 V supply, achieving a 1-dB compression point dynamic range of 43 dB, while the total output noise integrated over the passband is -70.5 dBm. The Q-tuning loop uses a resonator, which replicates those in the filter, as a voltage-controlled oscillator, and a conductance reference, rather than the conventional voltage reference, to achieve better controllability. The tuning system draws 14 mA from the power supply. The whole design occupies an area of 1.5/spl times/1.5 mm/sup 2/. The chip has been fabricated in the UMC, standard CMOS, 0.18 /spl mu/m process.

A VCF Loss-Control Tuning Loop for

A loss-control tuning loop for Q-enhanced LC filters based on a voltage-controlled filter (VCF) is presented. The main factors affecting the tuning accuracy in this tuning scheme, including mismatches and frequency tuning errors, are discussed. The tuning scheme was implemented for a 1.5-V, 6-GHz Q-enhanced LC filter on a UMC 0.18-mum standard CMOS process. The design and measurement results are given. Effective loss control of the filter over process tolerances is demonstrated

Q

To demonstrate the capabilities and synergy of the proposed ultra-low voltage design techniques in Chapters 2 and 3, we designed a 5th-order low-pass elliptic filter with a 135 kHz cut-off frequency. For minimum sensitivity requirements, a leap-frog topology was used. The design in [74] was frequency-scaled to 135 kHz, such that the signal amplitude maxima at all OTA outputs are at the same level. The filter characteristics has a pass-band ripple of 0.1 dB, a stop-band rejection of at least 35 dB, and two zeros in the stop-band – at 180 kHz and at 280 kHz. To obtain an accurate transfer characteristic, the OTA should have substantial open-loop gain all the way to 280 kHz, the second zero of the filter. The proposed amplifier has a worst-case gain of 20 dB at 280 kHz, which is sufficient. The filter resistors and capacitors were scaled so that the total noise contributions from the OTAs and from the resistors, integrated in the pass-band, are equal.

-Enhanced LC Filters

This chapter discusses low-voltage conventional receiver front-end circuits in the Radio-Frequency (RF) range, namely low-noise amplifiers (LNAs) and mixers, expanding on previous work [25, 26, 100–102]. For our study, we chose a future standard CMOS technology nanoscale node, expected by The International Technology Roadmap for Semiconductors [1] to have a supply voltage of 0.5 V, and a transistor threshold voltage of about 200 mV. In the first part of this chapter we consider design of stand-alone communication circuits . Then, we present design and measured results of a 900 MHz integrated receiver front end.

A 0.5 V 5th-Order Low-Pass Elliptic Filter

The ability to track and then sample an analog signal is an essential function in many signal acquisition interfaces. In such interfaces, analog waveforms need to be sampled and held to within the accuracy of the system, prior to quantization by either sequential or parallel means. In pipelined A/D converters, e.g. in [76], the input signal sample has to be held constant over the duration of each step in the A/D operation. As such, track-and-hold (T/H) circuits are regularly used in an analog-todigital (A/D) converter.

0.5 V Receiver Front-End Circuits

In this chapter an audio-band continuous-time (CT) ΣΔ modulator is presented as another example of true low voltage design without using low threshold devices or internal voltage boosting. A ΣΔ modulator has a higher level of design complexity than the circuit examples presented in the previous chapters. It requires a clocked comparator and feedback digital-to-analog converters (DAC) in addition to a loop filter of either continuous-time or discrete-time type.

A 0.5 V Track-and-Hold (T/H) Circuit

An amplifier is often a fundamental building block of an analog circuit. Fully differential circuits are widely used due to their large available signal swing, and superior supply and substrate interference immunity. In this chapter we will develop the design of fully differential amplifiers, which will be primary building blocks for subsequent designs at a 0.5 V supply voltage. As discussed earlier in Section 1.1, the realization of a low output impedance is required for the implementation of an operational amplifier. The unavailability of the common-drain stage, as seen in Fig. 1.3(b), makes this difficult, and hence we will only discuss the implementation of operational transconductance amplifiers (OTAs).