Nghia Van Phan

A 0.2 /spl mu/m 1.8 V SOI 550 MHz 64 b PowerPC microprocesser with copper interconnects

A 64 b PowerPC RISC microprocessor is incorporated in a 0.2 /spl mu/m CMOS technology with copper interconnects and multi-threshold transistors and next into a silicon-on-insulator (SOI) version of the same technology. Some architectural changes improve CPI, including doubling the L1 instruction and data caches to 128 kB and adding a 256 kB L2 directory. The total transistor count increased from 12 M to 34 M.

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits

Systems-on-chips (SoCs) that combine digital and high-speed communication circuits present new opportunities for power-saving designs. This results from both the large number of system specifications that can be traded off to minimize overall power and the inherent low capacitance of densely integrated devices. As shown in this paper, aggressively scaled silicon-on-insulator (SOI) CMOS is a promising technology for SoCs for several reasons: Transistor scaling leads to active power reduction in the sub-50-nm-channel-length regime, standard interconnect supports the high-quality passive devices essential to communications circuitry, and high-speed analog circuits on SOI are state of the art in terms of both performance and power dissipation. We discuss the migration of a complete digital circuit library from bulk to SOI to prove that SOI CMOS supports ASIC-style as well as fully custom circuit design.

A 660 MHz 64b SOI processor with Cu interconnects

The 64b PowerPC RISC microprocessor previously described is migrated from a 0.22 /spl mu/m SOI technology to a 0.18 /spl mu/m SOI technology. Key features of the 0.77 scaled 1.5 V technology are 0.08 /spl mu/m NFET channel lengths, 7 layer Cu metallization with low-/spl epsiv/ dielectric, low dose SOI substrate for improved material quality and productivity, and local interconnect. Dual gate oxide provides high I/O voltage compatibility. As this chip is a migration only 6 levels of metal and stacked devices for high voltage I/O were used.

AS/400 PowerPC compatible semi-custom technology

This paper describes the technology and semi-custom design aspects of the AS/400 PowerPC chip set. In order to meet the growing demand for AS/400 system performance, a 6 ns cycle time was specified. This requirement, coupled with the desire for a short development cycle, drove the chip team to choose a semi-custom design style utilizing a mature BICMOS technology. Three semi-custom chips and one ASIC were designed and packaged in a multi-chip, high performance package to form the processor engine.<<ETX>>

A 3.4 ns 0.8 /spl mu/m BiCMOS 53/spl times/53 b multiplier tree

A 53/spl times/53 b multiplier tree with 3.4 ns latency, 10 mm/sup 2/ active area, and 5 W power dissipation at 200 MHz and 3.6 V supply is implemented in 0.8 /spl mu/m n-well BiCMOS with 115 /spl Aring/ gate oxide, 0.45 /spl mu/m effective channel length, and 4 levels of metal. This 3.4ns low-latency multiplier is for a floating-point unit (FPU) on a BiCMOS RISC processor capable of performing IEEE double precision multiply-add operations in three pipelined stages at 200MHz (15ns latency, 5ns throughput, 400MFLOPs peak rate) using multiply-add fused dataflow.<<ETX>>