Salvatore N. Storino

A 0.2 /spl mu/m 1.8 V SOI 550 MHz 64 b PowerPC microprocesser with copper interconnects

A 64 b PowerPC RISC microprocessor is incorporated in a 0.2 /spl mu/m CMOS technology with copper interconnects and multi-threshold transistors and next into a silicon-on-insulator (SOI) version of the same technology. Some architectural changes improve CPI, including doubling the L1 instruction and data caches to 128 kB and adding a 256 kB L2 directory. The total transistor count increased from 12 M to 34 M.

A commercial multithreaded RISC processor

Implementation of a coarse-grained hardware-multithreaded processor for use in the IBM AS1400 uses a PowerPC architecture that supports two threads. Hardware multithreading is a technique for tolerating memory latency by utilizing otherwise idle cycles in the CPU. This requires the replication of the processor architecture registers for each thread. Replication is not required for the majority of processor logic such as instruction cache, data cache, TLB, instruction fetch and dispatch mechanisms, branch units, fixed-point units, floating-point units, and storage-control units.

A 660 MHz 64b SOI processor with Cu interconnects

The 64b PowerPC RISC microprocessor previously described is migrated from a 0.22 /spl mu/m SOI technology to a 0.18 /spl mu/m SOI technology. Key features of the 0.77 scaled 1.5 V technology are 0.08 /spl mu/m NFET channel lengths, 7 layer Cu metallization with low-/spl epsiv/ dielectric, low dose SOI substrate for improved material quality and productivity, and local interconnect. Dual gate oxide provides high I/O voltage compatibility. As this chip is a migration only 6 levels of metal and stacked devices for high voltage I/O were used.