Peiqi Xuan

Sub-20 nm CMOS FinFET technologies

A simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET (1999, 2000). Two different patterning approaches-e-beam lithography and spacer lithography-are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improve drive current.

Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime

Thin-body transistors with silicide source/drains were fabricated with gate-lengths down to 15 nm. Complementary low-barrier silicides were used to reduce contact and series resistance. Minimum gate-length transistors with T/sub ox/=40 /spl Aring/ show PMOS |I/sub dsat/|=270 /spl mu/A//spl mu/m and NMOS |I/sub dsat/|=190 /spl mu/A//spl mu/m with V/sub ds/=1.5 V, |V/sub g/-V/sub t/|=1.2 V and, I/sub on//I/sub off/>10/sup 4/. A simple transmission model, fitted to experimental data, is used to investigate effects of oxide scaling and extension doping.

FinFET SONOS flash memory for embedded applications

FD-SOI (fully depleted silicon-on-insulator) FinFET SONOS flash memory devices are investigated for the first time, and they are found to be scalable to a gate length of 40 nm. Although the FinFET SONOS device does not have a body contact, excellent program/erase characteristics are achieved, together with high endurance, long retention time and low reading disturbance. Devices fabricated on [100] and [110] silicon surfaces are compared.

Nanoscale ultra-thin-body silicon-on-insulator P-MOSFET with a SiGe/Si heterostructure channel

We report the concept and demonstration of a nanoscale ultra-thin-body silicon on-insulator (SOI) P-channel MOSFET with a Si/sub 1-x/Ge/sub x//Si heterostructure channel. First, a novel lateral solid-phase epitaxy process is employed to form an ultra-thin-body that suppresses the short-channel effects. Negligible threshold voltage roll-off is observed down to a channel length of 50 nm. Second, a selective silicon implant that breaks up the interfacial oxide is shown to facilitate unilateral crystallization to form a single crystalline channel. Third, the incorporation of SiGe in the channel resulted in a 70% enhancement in the drive current.

Design analysis of thin-body silicide source/drain devices

The use of complementary low-barrier silicides is investigated for reducing the series resistance of thin-body silicon-on-insulator (SOI) devices. Two different thin-body device types are simulated, one in which the source/drain regions are formed by the silicide without doping, and another in which the silicide source/drains are terminated by a doped extension region.

60 nm planarized ultra-thin body solid phase epitaxy MOSFETs

The continuous scaling of MOSFET technology into the deep sub-micron regime poses considerable challenge to the conventional MOSFET structure. To suppress short-channel effects such as DIBL and V/sub t/ roll-off, extremely high levels of channel doping are required, but these result in increased leakage and degraded mobility. Simulation shows that the ultra-thin body MOSFET is a promising alternative structure that effectively suppresses DIBL and other short channel effects. The channel film thickness required is typically 30% of the gate length. The most difficult step for fabrication of the ultra-thin body FET is the formation of a uniform thin channel film. Oxidation and etch back have been proposed, but are limited by thickness uniformity of the starting SOI wafers and by process-induced variation. On the other hand, deposited films can be well controlled and have good uniformity, so finding ways to deposit highly uniform channel material is very plausible. Solid phase epitaxy (SPE) has been reported for fabrication of sub-100 nm devices (Subramanian et al, 1999). In SPE, the thin film is formed by lateral crystallization of an amorphous deposited silicon film, giving precise control over channel thickness. In this paper, 60 nm planarized SPEFETs with excellent performance are reported. The effect of different trench sizes is investigated. Both single sided and two sided crystallization on the channel film is also studied.

Investigation of NiSi and TiSi as CMOS gate materials

NiSi is a promising new candidate for CMOS gate metal material because its workfunction can be adjusted by the implantation of dopants into the silicon before silicidation. In this report, NiSi and TiSi are studied, and the work functions of each are found to be adjustable over a wider range than previously published. This range covers the work function values required to achieve correct threshold voltages (V/sub t/) for both deep-scaled bulk CMOS and fully depleted, silicon-on-insulator MOSFETs. The influence of these silicides on the gate oxide and interface quality is also examined thoroughly via measurements of capacitance, minority carrier mobility, and gate-leakage current. While no degradation of the interface is observed with NiSi gates, TiSi gates generate interface traps and significantly degrade transistor device performance. With all the merits of a metal gate and no apparent degradation of interface quality, NiSi can be integrated with minor modification into a standard CMOS process and is a promising gate metal material for future CMOS technology generations.

Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel

Thin-body p-channel MOS transistors with a SiGe/Si heterostructure channel were fabricated on silicon-on-insulator (SOI) substrates. A novel lateral solid-phase epitaxy process was employed to form the thin-body for the suppression of short-channel effects. A selective silicon implant that breaks up the interfacial oxide was shown to facilitate unilateral crystallization to form a single crystalline channel. Negligible threshold voltage roll-off was observed down to a gate length of 50 nm. The incorporation of Si/sub 0.7/Ge/sub 0.3/ in the channel resulted in a 70% enhancement in the drive current. This is the smallest SiGe heterostructure-channel MOS transistor reported to date. This is also the first demonstration of a thin-body MOS transistor incorporating a SiGe heterostructure channel.

Comparison of short-channel effect and offstate leakage in symmetric vs. asymmetric double gate MOSFETs

Double gate MOSFETs (DGFETs) in the sub-0.1 /spl mu/m regime are unlikely to use channel doping to set the threshold voltage, V/sub t/. Therefore, work function engineering is required to properly set V/sub t/. Asymmetric DGFETs use one n/sup +/ and one p/sup +/-poly gate to achieve a reasonable threshold voltage (Tanaka et al., 1994), whereas symmetric DGFETs use the same near-midgap material for both gates. This results in significantly different energy-band diagrams. The on-state drive currents in these two structures have been shown to be comparable to each other if off-state leakage currents are balanced; in the on-state, the asymmetric DGFET matches the inherent two-channel advantage of the symmetric DGFET with a single dynamic-threshold channel (Kim and Fossum, 1999). However, their short-channel effects should differ, since the two structures have different leakage paths. In this paper, the MEDICI 2D device simulator is used to study off-state leakage current in NMOS DGFETs as a function of channel length. The short-channel leakage behavior is explained by analyzing the change in the channel potential barrier.

Characterization of the ultrathin vertical channel CMOS technology

In this paper, an ultrathin vertical channel (UTVC) CMOS with self-aligned asymmetric lightly doped drain is experimentally demonstrated. In the structure, the UTVC was obtained using solid phase epitaxy, and the midgap material, boron-doped poly-Si/sub 0.5/Ge/sub 0.5/, was used as the gate electrode to obtain symmetrical threshold voltages for both the NMOS and PMOS devices. Due to the ultrathin channel, the fabricated CMOS devices offer good immunity to short channel effects, and the typical subthreshold slopes of the 80 nm NMOS and PMOS are 102 mV/dec and 120 mV/dec, respectively. The fabricated CMOS inverters also show reasonable transfer characteristics. The UTVC CMOS technology provides a simple way to implement sub-100 nm devices for ULSI applications.