Nick van der Meijs

Simultaneous Analytic Area and Power Optimization for Repeater Insertion

We present an analytic formula for repeater insertion in globalinterconnects that simultaneously minimizes silicon device areaand power dissipation for a given performance ¿{crit}/K where ¿{crit}is the minimum possible delay along a global interconnect, withrepeaters inserted, and 0 < K ¿ 1. Given a certain wire geometry(width and layer assignment) and a factor K, we derive repeatersizes and segment lengths that simultaneously minimize silicon devicearea and power dissipation associated with the global signal.The analytic model requires only basic device and interconnectcharacterization data that are easily obtained. The results con£rmthat the absolute optimal performance is expensive in terms of areaand power. For example, 85% of performance requires only 30%of the area and 67% of the power compared to the best performance,reached in the unconstrained case. We have developed apareto-optimal repeater insertion theory based on this analyticalformulation. Besides exploring optimal area, power and performancetrade-offs for uniform buffer insertion, this tool can be usedfor the screening of critical segments when the buffers are position-constrained.

RDE-based transistor-level gate simulation for statistical static timing analysis

Existing industry-practice statistical static timing analysis (SSTA) engines use black-box gate-level models for standard cells, which have accuracy problems as well as require massive amounts of CPU time in Monte-Carlo (MC) simulation. In this paper we present a new transistor-level non-Monte Carlo statistical analysis method based on solving random differential equations (RDE) computed from modified nodal analysis (MNA). In order to maintain both high accuracy and efficiency, we introduce a simplified statistical transistor model for 45nm technology and below. The model is combined with our new simulation-like engine which can do both implicit non-MC statistical simulation and deterministic simulation fast and accurately. The statistics of delay and slew are calculated by means of the proposed analysis method. Experiments show the proposed method is both run time efficient and very accurate.

Thermal analysis of 3D integrated circuits based on discontinuous Galerkin finite element method

Even though vertical 3D integration offers increased device density, reduced signal delay, and design flexibility, heat and thermal concerns are, nevertheless, aggravated. In this context, accurate computation of temperature profile is required to establish thermal design rules governing the feasibility of integration options. Within this framework, a novel methodology based on discontinuous Galerkin finite element method for accurate thermal profile estimation of 3D integrated circuits is proposed. The method is utilized to simulate geometrically complicated physical structures with limited complexity overhead.

A 3.72μW ultra-low power digital baseband for wake-up radios

In order to minimize power consumption without sacrificing much latency performance, wake-up radios are employed to assist the main radio for low power channel monitoring. This paper presents the design and implementation of an ultra-low power digital baseband (DBB) circuit for a wake-up radio. In a 90nm CMOS process, the circuit running at a 800kHz clock consumes 3.72μW with a standard 1.2V supply voltage, and achieves very good packet detection performance. The circuit is fully functional at 0.6V supply consuming 0.9μW.

Dynamic Thermal Estimation Methodology for High-Performance 3-D MPSoC

In 3-D integrated circuits, accurate runtime sensing of on-chip temperature is required to establish dynamic thermal management instruction sets. Placement restrictions and excessive runtime thermal variations, however, compromise the performance and reliability of the sensor readings. Within this framework, a novel methodology for thermal estimation based on unscented Kalman filter, augmented only with a limited number of temperature sensors at a few selected locations, is proposed. In addition, we extend discontinuous Galerkin finite-element method to include coupling mechanism between neighboring grid cells for accurate thermal profile estimation and introduce a balanced stochastic truncation to find a low-dimensional but accurate approximation of the thermal network over the whole frequency domain. As the experimental results show, the runtime thermal estimation method reduces temperature estimation errors by an order of magnitude.

Statistical delay calculation with Multiple Input Simultaneous Switching

The increasing process variations which goes along with the continuing CMOS technology shrinking necessitate accurate statistical timing analysis. Multiple Input Simultaneous Switching (MISS) is simplified to Single Input Switching (SIS) in most of the recent approaches, which introduces significant errors in Statistical Static Timing Analysis (SSTA). Hence, we propose a new modeling and statistical analysis method to capture statistical gate delay variations, able to accurately handle MISS. Experiment results obtained with a 45nm technology show that our approach accurately obtains not only mean and standard deviation, but also the third moment, skewness.

Fast statistical analysis of RC nets subject to manufacturing variabilities

This paper proposes a highly efficient methodology for the statistical analysis of RC nets subject to manufacturing variabilities, based on the combination of parameterized RC extraction and structure-preserving parameterized model order reduction methods. The sensitivity-based layout-to-circuit extraction generates first-order Taylor series approximations of resistances and capacitances with respect to multiple geometric parameter variations. This formulation becomes the input of the parameterized model order reduction, which exploits the explicit parameter dependence to produce a linear combination of multiple non-parameterized transfer functions weighted by the parameter variations. Such a formulation enables a fast computation of statistical properties such as the standard deviation of the transfer function given the process spreads of the technology. Both the extraction and the reduction techniques avoid any parameter sampling. Therefore, the proposed method achieves a significant speed up compared to the Monte Carlo approaches.

Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver

To improve the accuracy of static timing analysis, the traditional nonlinear delay models are increasingly replaced by more physical gate models, such as current source models and transistor-level gate models. However, the extension of these accurate gate models for statistical timing analysis is still challenging. In this paper, we propose a novel statistical timing analysis method based on transistor-level gate models. The accuracy and efficiency are obtained by using an efficient random differential equation based solver. The correlations among signals and between input signals and delay are fully accounted for. In contrast to Monte Carlo simulation solutions, the variational waveforms for statistical delay calculation are obtained by simulating only once. At the end of statistical timing analysis, both the statistical delay moments and the variational waveforms are available. The proposed algorithm is verified with standard cells and ISCAS85 benchmark circuits in a 45-nm technology. The experimental results indicate that the proposed method can capture multiple input simultaneous switching for statistical delay calculation, and can provide 0.5% error for delay mean and 2.7% error for delay standard deviation estimation on average. The proposed statistical simulation introduces a small runtime overhead with respect to static timing analysis runtime. The MATLAB implementation of the proposed algorithm has two orders of magnitude speedup, compared to Spectre Monte Carlo simulation.

Considering Crosstalk Effects in Statistical Timing Analysis

The impact of crosstalk effects on timing performance is increasing as the device geometries are shrinking. As a consequence, crosstalk effects need to be considered in statistical timing analysis for higher accuracy. In this letter, the statistical interconnect delay due to crosstalk effects is calculated based on a piecewise linear delay change curve model (PLDM), which enables fast closed-form analytical delay evaluation. The PLDM-based method is independent of the delay change characteristics and is able to handle both Gaussian and non-Gaussian input skew distributions. The proposed method can be integrated into a statistical timing analyzer with runtime proportional to the number of samples for PLDM characterization. Experimental results demonstrate that the proposed method can estimate the delay mean and standard deviation for coupled RC interconnects at PTM 65-nm technology with errors better than -0.07% and -1.23%, respectively, with only 20 samples for PLDM characterization. In addition, the proposed method typically achieves two to three orders of magnitude speedup compared to Monte Carlo simulations.

Transistor-level gate model based statistical timing analysis considering correlations

To increase the accuracy of static timing analysis, the traditional nonlinear delay models (NLDMs) are increasingly replaced by the more physical current source models (CSMs). However, the extension of CSMs into statistical models for statistical timing analysis is not easy. In this paper, we propose a novel correlation-preserving statistical timing analysis method based on transistor-level gate models. The correlations among signals and between process variations are fully accounted for. The accuracy and efficiency are obtained from statistical transistor-level gate models, evaluated using a smart Random Differential Equation (RDE)-based solver. The variational waveforms are available, allowing signal integrity checks and circuit optimization. The proposed algorithm is verified with standard cells, simple digital circuits and ISCAS benchmark circuits in a 45 nm technology. The results demonstrate the high accuracy and speed of our algorithm.