Michel Berkelaar

Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs

A time-domain methodology for statistical simulation of nonlinear dynamic integrated circuits with arbitrary excitations is presented. The statistical behavior of the circuits is described as a set of stochastic differential equations rather than estimated by a population of realizations and Gaussian closure approximations are introduced to obtain a closed form of moment equations. Statistical simulation of specific circuits shows that the proposed numerical methods offer accurate and efficient solution of stochastic differentials for variability and noise analysis of integrated circuits.

RDE-based transistor-level gate simulation for statistical static timing analysis

Existing industry-practice statistical static timing analysis (SSTA) engines use black-box gate-level models for standard cells, which have accuracy problems as well as require massive amounts of CPU time in Monte-Carlo (MC) simulation. In this paper we present a new transistor-level non-Monte Carlo statistical analysis method based on solving random differential equations (RDE) computed from modified nodal analysis (MNA). In order to maintain both high accuracy and efficiency, we introduce a simplified statistical transistor model for 45nm technology and below. The model is combined with our new simulation-like engine which can do both implicit non-MC statistical simulation and deterministic simulation fast and accurately. The statistics of delay and slew are calculated by means of the proposed analysis method. Experiments show the proposed method is both run time efficient and very accurate.

Statistical delay calculation with Multiple Input Simultaneous Switching

The increasing process variations which goes along with the continuing CMOS technology shrinking necessitate accurate statistical timing analysis. Multiple Input Simultaneous Switching (MISS) is simplified to Single Input Switching (SIS) in most of the recent approaches, which introduces significant errors in Statistical Static Timing Analysis (SSTA). Hence, we propose a new modeling and statistical analysis method to capture statistical gate delay variations, able to accurately handle MISS. Experiment results obtained with a 45nm technology show that our approach accurately obtains not only mean and standard deviation, but also the third moment, skewness.

Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver

To improve the accuracy of static timing analysis, the traditional nonlinear delay models are increasingly replaced by more physical gate models, such as current source models and transistor-level gate models. However, the extension of these accurate gate models for statistical timing analysis is still challenging. In this paper, we propose a novel statistical timing analysis method based on transistor-level gate models. The accuracy and efficiency are obtained by using an efficient random differential equation based solver. The correlations among signals and between input signals and delay are fully accounted for. In contrast to Monte Carlo simulation solutions, the variational waveforms for statistical delay calculation are obtained by simulating only once. At the end of statistical timing analysis, both the statistical delay moments and the variational waveforms are available. The proposed algorithm is verified with standard cells and ISCAS85 benchmark circuits in a 45-nm technology. The experimental results indicate that the proposed method can capture multiple input simultaneous switching for statistical delay calculation, and can provide 0.5% error for delay mean and 2.7% error for delay standard deviation estimation on average. The proposed statistical simulation introduces a small runtime overhead with respect to static timing analysis runtime. The MATLAB implementation of the proposed algorithm has two orders of magnitude speedup, compared to Spectre Monte Carlo simulation.

Transistor-level gate model based statistical timing analysis considering correlations

To increase the accuracy of static timing analysis, the traditional nonlinear delay models (NLDMs) are increasingly replaced by the more physical current source models (CSMs). However, the extension of CSMs into statistical models for statistical timing analysis is not easy. In this paper, we propose a novel correlation-preserving statistical timing analysis method based on transistor-level gate models. The correlations among signals and between process variations are fully accounted for. The accuracy and efficiency are obtained from statistical transistor-level gate models, evaluated using a smart Random Differential Equation (RDE)-based solver. The variational waveforms are available, allowing signal integrity checks and circuit optimization. The proposed algorithm is verified with standard cells, simple digital circuits and ISCAS benchmark circuits in a 45 nm technology. The results demonstrate the high accuracy and speed of our algorithm.

Crosstalk-aware statistical interconnect delay calculation

As the device geometries are shrinking, the impact of crosstalk effects increases, which results in a stronger dependence of interconnect delay on the input arrival time difference between victim and aggressor inputs (input skew). The increasing process variations lead to statistical input skew which induces significant interconnect delay variations. Therefore, it is necessary to take input skew variation into account for interconnect delay calculation in the presence of process variations. Existing timing analysis tools evaluate gate and interconnect delays separately. In this paper, we focus on statistical interconnect delay calculation considering crosstalk effects. A piecewise linear delay-change-curve model enables closed-form analytical evaluation of the statistical interconnect delay caused by input skew (SK) variations. This method can handle arbitrarily distributed SK variations. The process-variation (PV)-induced interconnect delay variation is handled in a quadratic delay model which considers coupling effects. The SK- and PV-induced interconnect delay variations are combined together for crosstalk-aware statistical interconnect delay calculation. The experimental results indicate that the proposed method can predict the interconnect delay impacted by both input skew variation and process variations with average (maximum) absolute mean error 0.25% (0.75%) and standard deviation error 1.31% (3.53%) for different types of coupled wires in a 65nm technology.

Transistor-level gate modeling for nano CMOS circuit verification considering statistical process variations

Equation- or table-based gate-levelmodels (GLMs) have been applied in static timing analysis (STA) for decades. In order to evaluate the impact of statistical process variabilities, Monte Carlo (MC) simulations are utilized with GLMs for statistical static timing analysis (SSTA), which requires a massive amount of CPU time. Driven by the challenges associated with CMOS technology scaling to 45nm and below, intensive efforts have been contributed to optimize GLMs for higher accuracy at the expense of enhanced complexity. In order to maintain both accuracy and efficiency at 45nm node and below, in this paper we present a gate model built from a simplified transistor model. Considering the increasing statistical process variabilities, the model is embedded in our new statistical simulation engine, which can do both implicit non-MC statistical as well as deterministic simulations. Results of timing, noise and power grid analysis are presented using a 45nm PTMLP technology.

Balanced Truncation of a stable non-minimal deep-submicron CMOS interconnect

As the widening of process variability in submicron CMOS technology calls for accurate timing models, their deployment requires well-controlled characterization techniques to cope with the complexity and scalability. In this context, model order reduction techniques have been used extensively to reduce the complexity of extracted interconnect circuits and to expedite fast and accurate circuit simulation. In the interconnect modeling, solving large-scale Lyapunov equations arises as a necessity in model order reduction techniques based on Balanced Truncation. In this paper, within this framework, dominant eigensubspaces of the product of the system Gramians are approximated directly. We construct orthogonal basis sets for the dominant subspaces of controllability and observability Gramians and perform eigenvalue decomposition to reduce the cost of singular value decomposition. As the experimental results indicate, the proposed approach can significantly reduce the complexity of interconnect, while retaining high accuracy in comparison to the original model.

Pseudo circuit model for representing uncertainty in waveforms

This paper introduces a novel compact implicit model for a probabilistic set of waveforms (PSoW) which arise as representations for uncertain signal waveforms in Statistical Static Timing Analysis (SSTA). In traditional SSTA tools, signals are just represented as (distributions of) arrival time and slew. In our approach, to increase accuracy, PSoWs are used instead. However, to represent PSoWs explicitly, a very large amount of data is necessary, which can be problematic. To solve this problem, a compact implicit model is introduced, which can be characterized with just a handful of parameters. The results obtained show that the implicit model can generate real-life PSoWs with high accuracy.

Statistical Moment Estimation of Delay and Power in Circuit Simulation

Monte Carlo methods and simulation are often used to estimate the mean, variance, and higher order statistical moments of circuit properties like delay and power. The main issues with Monte Carlo methods are the required long run time and the need for prior detailed knowledge of the distribution of the variations. Additionally, most of available circuit simulation tools can run Monte Carlo analysis for Gaussian, lognormal and uniform distribution only. In this paper, in order to estimate these statistical moments, we propose a new method based on a uniform sampling technique and a weighted sample estimator. The proposed method needs significantly fewer simulation runs, and does not need detailed prior knowledge of the variation distributions. Furthermore, it can be used for any type of probability distribution irrespective of the circuit simulation tool used for the analysis. The results obtained shows that the proposed method needs 100× fewer simulations iterations than Monte Carlo runs for accurate moments estimation of delay and power for standard cells in 45nm and 32nm technologies. Keywards Delay, Power, STA, SSTA, Monte Carlo, Statistical Analysis