Rene van Leuken

MB-LITE: a robust, light-weight soft-core implementation of the MicroBlaze architecture

Due to the ever increasing number of microprocessors which can be integrated in very large systems on chip the need for robust, easily modifiable microprocessors has emerged. Within this paper a light-weight cycle compatible implementation of the MicroBlaze architecture called MB-LITE is presented in an attempt to fill the gap in quality between commercial and open source processors. Experimental results showed that MB-LITE obtains very high performance compared with other open source processors while using very few hardware resources. The microprocessor can be easily extended with existing IP thanks to an easily configurable data memory bus and a wishbone bus adapter. All components are modular to optimize design reuse and are developed using a two-process design methodology for improved performance, simulation and synthesis speeds. All components have been thoroughly tested and verified on a FPGA. Currently an architecture with four MB-LITE cores in a NoC architecture is in development which will be implemented in 90nm process technology.

Extracting behavior and dynamically generated hierarchy from SystemC models

We present a novel approach to extract the dynamically generated module hierarchy and its behavior from a SystemC model. SystemC is a popular modeling language which can be used to specify systems at a high ab]ion level. The module hierarchy of a SystemC model is dynamically constructed during the execution of the elaboration phase of the model. This means that a system designer can build regular structures using loops and conditional statements. Currently, most SystemC tools can not cope with SystemC models for which the module hierarchy depends on dynamic parameters. In our approach this hierarchical information is retrieved by controlling and monitoring the executing of the elaboration phase of the model using a GDB debugger. Thereafter, the behavioral information is retrieved by using a GCC plug-in. This plug-in produces ab] syntax trees in static single assignment form. This behavioral information is linked with the hierarchical information. Our approach is completely non-intrusive. The SystemC model and the SystemC reference implementation can be used without any modification. We have implemented our approach in a SystemC front-end called SHaBE (SystemC Hierarchy and Behavior Extractor). This front-end facilitates the development of future SystemC visualization, debugging, static verification, and synthesis tools.

Thermal analysis of 3D integrated circuits based on discontinuous Galerkin finite element method

Even though vertical 3D integration offers increased device density, reduced signal delay, and design flexibility, heat and thermal concerns are, nevertheless, aggravated. In this context, accurate computation of temperature profile is required to establish thermal design rules governing the feasibility of integration options. Within this framework, a novel methodology based on discontinuous Galerkin finite element method for accurate thermal profile estimation of 3D integrated circuits is proposed. The method is utilized to simulate geometrically complicated physical structures with limited complexity overhead.

A 3D Network-on-Chip for stacked-die transactional chip multiprocessors using Through Silicon Vias

Effective utilization of computing power offered by modern chip multiprocessors (CMP) depends on the design and performance of the interconnect that connects them. We present a three-dimensional Network-on-Chip (NoC) based on the R3 router architecture for transactional CMPs utilizing advanced Through Silicon Vias (TSV) in a stacked-die architecture, facilitating low latency and high throughput communication between CMP nodes. We report the performance of an R3 based three-dimensional mesh in a stacked-die transactional CMP highlighting the limitations of performance scale-up with stacking. Furthermore, we present data on area penalty associated with the use of TSVs in different configurations in 90nm UMC technology.

A precise SystemC-AMS model for Charge Pump Phase Lock Loop with multiphase outputs

SystemC-AMS as an extension of SystemC provides the essential capability to describe a mix-signal heterogeneous system, so that a virtual-prototype model can be generated to help analyze a whole mix-signal system and further guide the circuit design. This paper presents an example of systemC-ams modeling for a 10 phase 500 MHz charge pump phase lock loop, including digital models like phase/frequency detector and clock N-divider, and analog models like charge pump, low pass filter and voltage controlled oscillator. In order to prove the models accuracy, the SPICE simulation result from the corresponding CMOS circuits based on the same structure of these models is used for comparison, and PLL systemC-AMS model is validated1.

System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs

Modern 3-D multiprocessor systems-on-chip (MP-SoC) incorporate processing elements (PEs) and memories within die-stacks interconnected using through-silicon vias (TSVs). The resulting power density of these systems necessitates the inclusion of thermal effects in the architecture space exploration stage of the design process. The number and placement of TSVs influences the thermal conductivity in the vertical direction in die-stacks, and consequently these must be considered during thermal analysis. However, the special requirement of keep out zones (KOZs) for TSVs due to mechanical stress considerations complicates the design of the vertical interconnect, potentially impacting its electrical performance as well. This paper presents an integrated methodology that allows for TSV topology exploration to evaluate the best vertical interconnect structure while considering crosstalk, area overheads, and KOZ requirements using an initial system floorplan. After incorporating feedback from the exploration, the resulting vertical interconnect is included within a temperature-power simulation that estimates the thermal profile of the 3-D stack. Within this methodology, a novel power management scheme for 3-D MP-SoCs that considers both temperature as well as positional information and thermal relationships between PEs, while performing dynamic voltage-frequency scaling (DVFS), is introduced. The scheme effectively maintains smooth temperature profiles, decreases fluctuations in voltage-frequency levels, and increases the aggregate frequency of operation at a lower total power dissipation. Further, the scheme is applied to a stack partitioned into voltage islands, where it is shown to match the conventional per-core DVFS schemes in its performance.

Dynamic Thermal Estimation Methodology for High-Performance 3-D MPSoC

In 3-D integrated circuits, accurate runtime sensing of on-chip temperature is required to establish dynamic thermal management instruction sets. Placement restrictions and excessive runtime thermal variations, however, compromise the performance and reliability of the sensor readings. Within this framework, a novel methodology for thermal estimation based on unscented Kalman filter, augmented only with a limited number of temperature sensors at a few selected locations, is proposed. In addition, we extend discontinuous Galerkin finite-element method to include coupling mechanism between neighboring grid cells for accurate thermal profile estimation and introduce a balanced stochastic truncation to find a low-dimensional but accurate approximation of the thermal network over the whole frequency domain. As the experimental results show, the runtime thermal estimation method reduces temperature estimation errors by an order of magnitude.

Low Overhead Message Passing for High Performance Many-Core Processors

Many-core processors provide the raw computation power required by modern high-performance multimedia and signal processing workloads. The translation of this into execution performance is often constrained by the overheads of communication between concurrent tasks. This paper presents Pronto, a low overhead message passing system which simplifies the semantics of data movement between communicating tasks by performing buffer management, message synchronization and address translation directly in hardware. The integration of these functions into hardware results in transfer latencies up to 30% shorter than state of the art MPI derivatives. The overheads for communication in a 16-core processor array are under 5% for 64-word burst transfers with Pronto using workloads such as the JPEG decoder and FIR filter. Furthermore, this paper also studies the effect of task mapping and interconnect traffic on the predictability of data block arrival times, and illustrates a method to reduce variations.

Ctherm: An Integrated Framework for Thermal-Functional Co-simulation of Systems-on-Chip

This paper presents therm, an integrated framework for cycle-accurate thermal and functional evaluation of systems-on-chip. The presented framework enables accurate characterization of thermal behaviour by generating detailed physical models for components based on input specifications, and simulating them within a tightly integrated co-simulation platform with an embedded thermal simulator. Therms fine-grained modelling approach yields 70% higher accuracy in hotspot resolution as compared to conventional approaches that abstract component internals. Simulation runtime time is reduced by up to 36% over conventional continuous approaches through the use of thermal check pointing, enabling the fast-forwarding of thermal simulations without loss of thermal continuity.

Parallel Channel Estimator and Equalizer for Mobile OFDM Systems

Mobile OFDM refers to OFDM systems with fast moving transceivers, in contrast to traditional OFDM systems whose transceivers are stationary or have a low velocity. In this paper, we use the basis expansion model (BEM) to model time-varying OFDM channels. Using different BEM’s, we investigate various architectures to implement the least-squares (LS) channel estimation and its corresponding zero-forcing (ZF) channel equalization. The experimental results show that our implementation for mobile OFDM systems is capable of combatting the time variation of mobile OFDM channels, and more hardware resource utilization is necessary compared with a traditional OFDM design which fails in a time-varying scenario. For mobile OFDM systems, different BEM’s are available for the channel modeling. We observe that the so-called Critically sampled Complex-Exponential BEM (CCE-BEM) leads to the most efficient hardware architecture while still maintaining high modeling accuracy.