Nico Hellwege

Modeling of an analog recording system design for ECoG and AP signals

The recording of neural activities has turned out to be a promising approach to understand the basic function of specific brain parts like the visual or motor cortex. However, the development and design of advanced neural recording systems is very challenging since the number of parallel measurement channels increases continuously. Beside the analog recording channels digital preprocessing becomes mandatory to handle the corresponding amount of data and to adapt this data to the available transmission bandwidth. In this paper we present the design as well as the behavioral modeling of an analog recording front-end. Simulation and measurement results demonstrate the performances of the system for recording neural signals. Since simulation of this analog front-end is very time consuming but essential for large fully-integrated designs, a mixed-signal model approach is introduced that enables a significant simulation acceleration of integrated and external analog front-ends. The simulation can be accelerated by a factor of up to 22.2 for a single front-end. The proposed system has been fabricated in a 0.35 μm CMOS technology and performances have been measured. This demonstrates that the behavioral model is compatible to the transistor level design. A neural spike detector shows the transient performance of the modeled design on real input stimuli.

AAS-Maps: Aging-aware sensitivity-maps for reliability driven analog circuit design

Analog design is facing new challenges as reliability requirements are increasingly moving into focus for target specifications. Methods providing a degradation-aware design flow exist, but mostly involve algorithmic optimization and lack of computational efficiency and circuit insight. This paper proposes the use of aging-aware sensitivity maps generated by operating point-dependent degradation within the gm/Id scheme. Sensitivity values proof to be a good measure for circuit degradation. Different designs of a common source amplifier structure are investigated by comparing aging sensitivities and simulated degradation. The results show that in opposition to existing methods this technique enables aging-aware design during design phase with comparatively low computational effort.

Using operating point-dependent degradation and g m /I D method for aging-aware design

Effects like NBTI and HCI are degrading the characteristics of analog circuits. Available countermeasures to maintain system performances often include the use of optimizers or other external tools to size devices appropriately, which give no insight in relations between degradation and circuit parameters for the designer. This paper proposes an extension of the gm/ID sizing method by considering aged transistor parameters for fresh circuit design. A possible usage scenario for this investigation is given by optimizing a simple circuit towards higher reliability. The degradation in amplification of a common source amplifier is reduced by 19 % for a full time operation of 10 years.

Optimum Operating Points of Transistors with minimal Aging-Aware Sensitivity

Degradation of the threshold voltage in CMOS transistors affects the performance of analog circuits over time. In order to meet set target specifications, the influence of these degradation modes needs to be considered and compensated during the design phase. This work introduces an aging-aware sensitivity function, which allows the computation of optimum operating points of transistors, revealing circuits with a minimum degradation with respect to aging. A PMOS common source amplifier is designed by setting operating points of all relevant transistors according to the minimal sensitivity with respect to aging. The results show that for given target specification this method provides a well functional measure to reduce the degradation of circuit characteristics.

Analog behavioral modeling for age-dependent degradation of complex analog circuits

Analog circuit performance are degrading by effects like HCI and NBTI. These performance shifts need to be evaluated by the designer to meet given specifications. The evaluation on transistor level enables an accurate prediction of degradation behavior for a chosen circuit. However, this task is very time-consuming for complex analog circuitry. This paper proposes the use of response surface modeling for age-dependent degradation. The generated model is used to extend analog behavioral descriptions and for an accelerated system level analysis. The proposed age-dependent degradation model is demonstrated on a common source amplifier and an analog frontend for the measurement of neural activities. Simulation results demonstrate the accuracy and simulation acceleration of the proposed modeling method.

Reliability analysis for integrated circuit amplifiers used in neural measurement systems

NBTI and HCI are not only present in digital circuits but also in analog circuitry. Integrated circuit amplifiers as used in neural measurement systems (NMS) need to be resistive against degradation since these systems cannot be replaced easily. A topology driven design methodology to increase the reliability of amplifiers used for intracortical neural recording has been proposed in this work. This approach leads to a decrease in degradation for some system performances by a factor of three. It has been shown that the degradation of a circuit is highly dependent on the selected current mirror and biasing circuit.

Charge-based stochastic aging analysis of CMOS circuits

Scaled down CMOS transistors are prone to degradation and process variation. This necessitates a transistor model that provides an insight into the internal dependencies between these two crucial effects. Models for modern transistors and their degradation behavior are hardly attachable. This paper proposes a modified BSIM6 model which includes degradation due to BTI and HCI and in addition process variations. The application of this method is demonstrated on the basis of a single MOSFET and an inverter stage. The results can be used in the gm/Id work flow or for yield estimation on circuit level.

An aging-aware transistor sizing tool regarding BTI and HCD degradation modes

In this paper we present a tool based approach for an aging-aware design method. Extending the gm/ID sizing method by operating point-dependent degradation caused by BTI and HCD enables an innovative design flow. This design flow considers performance characteristics for a fresh circuit and also those of a degraded circuit at design time. Once the degradation from a single transistor is computed, the GMID-Tool does not need any further SPICE or aging simulation. The impact of the change in design methodology is shown for a typical differential amplifier structure.

A low-power wireless UHF/LF sensor network with web-based remote supervision — Implementation in the intelligent container

Vegetables, fruits and fish are very sensitive to variations in environmental conditions. To avoid a significant waste of goods during transportation the temperature and the humidity have to be set close to a predetermined point by the cooling unit of the container. Continuous and precise monitoring of physical parameters is therefore an important task to reduce the amount of spoiled goods. To supervise the container status the monitored data have to be evaluated and transmitted to the end-user. A graphical interface enables the setting and analysis of essential parameters and the supervision of the load quality. In this paper a low-power UHF / LF sensor system with a web-based remote supervision is presented. The system consists of wireless low power sensor nodes, a base station and corresponding antennas. A supervision unit is implemented for freight quality monitoring and for transmitting commands to dedicated sensor IDs. A web-based interface in combination with a virtual private network is used to establish a connection to the container and to control relevant parameters and evaluate data acquired by the sensor nodes.

Analysis of aging effects - From transistor to system level

Abstract Due to shrinking feature sizes in integrated circuits, additional reliability effects have to be considered which influence the functionality of the system. These effects can either result from the manufacturing process or external influences during the lifetime such as radiation and temperature. Additionally, modern technology nodes are affected by time-dependent degradation i.e. aging. Due to the age-dependent degradation of a circuit, processes on the atomic scale of the semiconductor material lead to charges in the oxide silicon interface of CMOS devices, altering the performance parameters of the device and subsequently the behavior of the circuit. With the continuous downscaling of modern semiconductor technologies, the impact of these atomic scale processes affecting the overall system characteristics becomes more and more critical. Therefore, aging effects need to be assessed during the design phase and actions have to be taken guaranteeing the correct system functionality throughout a systems lifetime. This work presents methods to investigate the influence of age-dependent degradation as well as process-variability on different levels. An operating-point dependent sizing methodology based on the g m / I D -method extended to incorporate aging, which aims at developing aging-resistent circuits is presented. Additionally, the sensitivity of circuit performances in regard to aging can be determined. In order to investigate the reliability of a complex system on behavioral level, a modeling method to represent the performance of system components in dependence of aging and process variability is introduced.