Theodor Hillebrand

Parameter identification for behavioral modeling of analog components including degradation

An analog systems performance can be influenced by many factors such as age-dependent degradation effects which need to be considered during the design process. Transistor level degradation analysis is very time-consuming for large and complex circuits. Behavioral models can be used to speed up the simulation and enable an evaluation on a higher abstraction level. In this paper, a structured method for the development of behavioral models is proposed. By using Response Surface Models to represent a systems key-performances, reliability analysis on system level is possible. A sensitivity analysis is used to identify the relevant parameters and to reduce the overall complexity of the model. The method is demonstrated on an amplifier and a voltage reference.

Online monitoring of NBTI and HCD in beta-multiplier circuits

Scaled down analog integrated circuits are prone to degradation. This necessitates an online degradation monitoring and sophisticated analysis of degradation for this circuitry. Voltage reference sources such as beta-multiplier are commonly used circuits to set the operating points for downstream circuitry. Thus, the degradation of these sources are crucial for the overall degradation. In this paper the simulation results of the degradation analysis of a beta-multiplier circuit including the startup circuit, implemented in a 65nm CMOS technology, considering the temperature, are shown. A new approach for online degradation monitoring is introduced, utilizing startup circuit components to ensure minimal area and power overhead.

Temperature- and aging-resistant inverter for robust and reliable time to digital circuit designs in a 65nm bulk CMOS process

Inverters are one of the most basic logic blocks and exhibit a strong temperature dependency. Additionally, degradation in CMOS transistors affects the performance of circuits over time and is strongly dependent on temperature during circuit operation. In order to design robust and reliable ring oscillators and time to digital converters, both temperature dependencies have to be considered. This work introduces a circuit design for a robust and resilient inverter and an analysis on its temperature-dependent aging characteristic. The implemented inverter is driven by a common-source amplifier to achieve high robustness against temperature variation and aging effects. Based on this, circuit designs for a ring oscillator and an inverter-based delay line for a time to digital converter has been implemented. The results show that the deviation of the delay for an inverter can be minimized from 13.2% for conventional inverter design to less than 2% for the temperature-and aging-resistant design over a wide temperature range from -40° C to 150° C and a stress time of ten years.

Degradation and temperature analysis of voltage-controlled ring oscillators for robust and reliable oscillator designs in a 65nm bulk CMOS process

Ring oscillators exhibit a strong temperature dependency. Additionally, degradation in CMOS transistors affects the performance of circuits over time and is strongly dependent on temperature during circuit operation. In order to design robust and reliable ring oscillator-based circuits, both temperature dependencies have to be considered. This work introduces systematic analyses on temperature dependencies for different voltage-controlled ring oscillators, which are based on current-starved inverters, and its temperature-dependent aging characteristics. The current-starved inverters are driven either by a common-source amplifier with non-linear control characteristic of the oscillation frequency with regard to input voltage or by a transconductance amplifier with linear control characteristic. The results show that the designer has to prioritise robustness and reliability over linear control characteristic or vice versa.

Charge-based stochastic aging analysis of CMOS circuits

Scaled down CMOS transistors are prone to degradation and process variation. This necessitates a transistor model that provides an insight into the internal dependencies between these two crucial effects. Models for modern transistors and their degradation behavior are hardly attachable. This paper proposes a modified BSIM6 model which includes degradation due to BTI and HCI and in addition process variations. The application of this method is demonstrated on the basis of a single MOSFET and an inverter stage. The results can be used in the gm/Id work flow or for yield estimation on circuit level.

Behavioral modeling of a sensor interface circuit including various non-idealities

In modern CMOS processes, several non-ideal influences affect the functionality of integrated circuits. In order to analyze and reduce these influences, time intensive circuit simulations are performed at transistor level. Although numerous non-idealities are considered in such simulations, they cannot be analyzed separately since they are inherent parts of the transistor models and cannot be faded out. In this work, a solution to this problem is presented: the use of Verilog-A/MS behavioral models in combination with Response Surface Modeling. Since error sources can easily be switched on and off in these models, their influence on circuit parameters can be examined individually. Moreover, the required simulation time is drastically reduced by using these models. A 65nm CMOS sensor interface is selected to demonstrate the advantages of the introduced approach. The interface is transferred from transistor to behavioral level before both circuit representations are compared in various simulations.

Design for reliability of generic sensor interface circuits

Abstract Numerous applications require the use of robust and reliable integrated circuits. In order to develop such circuits, a wide variety of influences need to be considered and also compensated if necessary. For a complete consideration of all reliability issues, the circuit has to be investigated on different levels of abstraction and together with the complete overlying system. These requirements are addressed in this work by using cross-layer design methods for the development of a generic sensor interface as an example for a complex integrated circuit. During the development, a reliability-aware design is used and major physical effects are taken into account, which alter the overall behavior of the system. Furthermore, modeling techniques are applied to port influences and circuit components from one level of abstraction to another. Possible countermeasures and compensation techniques for a reliable circuit design are also analyzed on transistor and system level. The result is a sensor interface circuit, which can be used to investigate all effects of interest and suitable countermeasures on different abstraction levels.

Variation- and degradation-aware stochastic behavioral modeling of analog circuit components

Process variation and aging effects influence the performances of integrated circuits in modern technology nodes. In this paper, a method is proposed to build a behavioral model to represent the influences of process variation, aging and operational parameters on circuit performances. The variability of performance is represented using distribution functions while Response Surface Models (RSM) are used to describe the dependence of the distributions moments on operational parameters. Compared to other approaches, less parameters have to be included in the RSM therefore reducing the complexity. This enables a fast Monte-Carlo analysis with aging analysis on a behavioral level. The method is evaluated for a voltage reference circuit and an operational amplifier showing a good representation of the variability and reaching a very good speedup of simulation time.

Design and Verification of Analog CMOS Circuits Using the g m / I D -Method with Age-Dependent Degradation Effects.

In this paper a tool based on the gm/ID-methodology is presented to provide information on operating point-dependent degradation in integrated circuits caused by NBTI and HCI during early design stages. The advantage of the presented GMID-Tool is that it does not require any further SPICE or aging simulations after the extraction of the fest and aged small signal parameters of a single transistor. Using the GMID-Tool, the design time of an integrated circuit is reduced significantly. In addition, the GMID-Tool is process-independent and universally applicable as it takes technology specific data as input. The verification of the GMID-Tool is shown at the example of a Common-Source Amplifier and a Miller-OTA.

Design and verification of analog CMOS circuits using the g m /I D -method with age-dependent degradation effects

In this paper a tool based on the g m /I D -methodology is presented to provide information on operating point-dependent degradation in integrated circuits caused by NBTI and HCI during early design stages. The advantage of the presented GMID-Tool is that it does not require any further SPICE or aging simulations after the extraction of the fest and aged small signal parameters of a single transistor. Using the GMID-Tool, the design time of an integrated circuit is reduced significantly. In addition, the GMID-Tool is process-independent and universally applicable as it takes technology specific data as input. The verification of the GMID-Tool is shown at the example of a Common-Source Amplifier and a Miller-OTA.