Nicolas Berard

Scan Design and Secure Chip

Testing a secure system is often considered as a severebottleneck. While testability requires to an increase inboth observability and controllability, secure chips aredesigned with the reverse in mind, limiting access to chipcontent and on-chip controllability functions. As a result,using usual design for testability techniques whendesigning secure ICs may seriously decrease the level ofsecurity provided by the chip. This dilemma is even moresevere as secure applications need well-tested hardwareto ensure that the programmed operations are correctlyexecuted. In this paper, a security analysis of the scantechnique is performed. This analysis aims at pointing outthe security vulnerability induced by using such a DfTtechnique. A solution securing the scan is finally proposed.

Scan design and secure chip [secure IC testing]

Testing a secure system is often considered as a severe bottleneck. While testability requires an increase in both observability and controllability, secure chips are designed with the reverse in mind, limiting access to chip content and on-chip controllability functions. As a result, using usual design for testability (DfT) techniques when designing secure ICs may seriously decrease the level of security provided by the chip. This dilemma is even more severe as secure applications need well-tested hardware to ensure that the programmed operations are correctly executed. In this paper, a security analysis of the scan technique is performed. This analysis aims at pointing out the security vulnerability induced by using such a DfT technique. A solution securing the scan is finally proposed.