Nicolas Delaunay

Linearization of a 65nm CMOS power amplifier with a Cartesian Feedback for W-CDMA standard

A study based on improving linearity of an integrated RF power amplifier (PA) has been done for W-CDMA standard. This power amplifier had been designed in 65nm CMOS of STMicroelectronics under Cadence. The chosen linearization technique is a Cartesian Feedback (CFB). Thanks to this linearization technique, the ACPR has been improved by 22dB at 5MHz from the carrier for an output power of 18dBm.

Design of a mixed-signal Cartesian Feedback loop for a low power zero-IF WCDMA transmitter

In this paper, an improved digital-stage design of a mixed-signal Cartesian Feedback loop for a zero-IF WCDMA transmitter is presented. The transmitter architecture consists of an analog stage including filters, I/Q modulator, feedback I/Q demodulator and a digital stage which adjusts the phase misalignment around the loop. We propose an optimized CORDIC design for the digital part in order to improve the system operating frequency without increasing the silicon surface area. ASIC synthesis proves that using a not fully pipelined CORDIC architecture allows us to reach 230 MHz with system power consumption under 4.3 mw which is two times less than a fully analog system.

Mixed Cartesian feedback for Zero-IF WCDMA transmitter

In this paper, a new adaptive power amplifier (PA) linearization technique is presented. The idea is to consider a classic WCDMA Zero-Intermediate Frequency (Zero-IF) transmitter with a modified Cartesian feedback (CFB) loop. The new transmitter architecture consists of an analog stage including forward I/Q modulator and feedback I/Q demodulator and a digital stage adjusting the phase rotation around the loop. The digital phase-alignment system consumes 2.94 mW (tree time less than a full-analog system).

A RF transmitter linearized using Cartesian Feedback in CMOS 65nm for UMTS standard

A fully CMOS transmitter including a power amplifier (PA) using a Cartesian Feedback (CFB) technique is presented. This system aims at improving the linearity of the transmitter, designed in 65nm CMOS technology from STMicroelectronics, essentially the power amplifier linearity. This transmitter delivers a maximum output power of 23dBm. Thanks to this linearization technique, the ACPR has been improved by 22dB at 5MHz from the carrier.

Cartesian Feedback with Digital Enhancement for CMOS RF Transmitter

The trend of communication systems with higher data rates requirescomplex modulation techniques. To satisfy the stringent linearityrequirements of the emitter, linearization techniques have attractedmuch attention. Many methods are proposed to reduce the effects ofnonlinearities. We implemented an analog and digital Cartesian feedbacktechnique in an integrated transmitter in 65-nm CMOStechnology. This approach offers flexibility and paves the way formulti-standard linearized RF transmitters.

Characterization methodology of a millimeter-wave 65nm CMOS PA dedicated to 60GHz WPAN standard

A millimeter-wave PA (Power Amplifier) based on a 65nm CMOS technology from STMicroelectronics has been designed. It is optimized to deliver the maximum OCP1 (Output Compression Point) equal to 12dBm. The targeted feature is the unlicensed band around 60GHz suitable for Wireless Personal Area Network application (WPAN). Considering that constraints, one-tone simulations are not sufficient to characterize the linearity performances of the PA in its real conditions of use. Consequently, the high frequency memory effect is firstly highlighted by performing two-tone simulations. Linearity figures of merit are discussed applying an OFDM (Orthogonal Frequency Devising Multiplexing) modulated signal. The PA offers an ACPR of 35dB, an EVM of 20%and compresses at 9dBm.