Sofiane Aloui

RF-pad, Transmission Lines and balun optimization for 60GHz 65nm CMOS Power Amplifier

Design and optimization of 65nm CMOS passive devices which are used in the implementation of a 60GHz Power Amplifier (PA) are presented. The targeted application is the low cost Wireless Personal Area Network (WPAN). A new optimized Radio Frequency (RF)-pad is used to minimize the losses of the PA access. The PA is matched via balun and Transmission Lines (T-Lines). T-Lines ensure both broadband inter-stage matching and biasing. S-parameters and large signal measurement results are demonstrated and compared with electromagnetic simulations. The PA achieves a maximum output power Psat of 7.3dBm with a gain of 8.5dB while consuming 96mA from a 1.2V supply. The active die area of the chip is 0.065mm2. Additionally, innovative technique is adopted in the balun design to improve the balanced-to-unbalanced mode conversion and PA performances.

A 60GHz, 13 dBm fully integrated 65nm RF-CMOS power amplifier

A 65 nm CMOS, 60 GHz fully integrated power amplifier (PA) from STMicroelectronics has been designed for low cost Wireless Personal Area Network (WPAN). It has been optimized to deliver the maximum linear output power (OCP1) without using parallel amplification topology. The simulated OCP1 is equal to 8.9 dBm with a gain of 8 dB. To obtain good performances and consume an ultra compact area of silicon, the PA has been matched and optimized with a mixed technique, using lumped and distributed elements. The chip size is 0.48 mm*0.6 mm including pads.

A 59GHz-to-67GHz 65nm-CMOS high efficiency Power Amplifier

A two-stage single-ended Power Amplifier (PA) is fabricated for the 60GHz Wireless Personal Area Network (WPAN) standard. It is based on the 65nm CMOS technology from STMicroelectronics. The PA is biased in class A and uses distributed elements to perform impedances matching. S-parameters and large signal simulations are validated by measurement results. Load pull measurements are performed to get the best operation of the PA. It achieves a saturated output power (Psat) of 12dB and offers Power Added Efficiency (PAE) of 15%. The die area is 0.29mm2 with pads.

Optimized pad design for millimeter-wave applications with a 65nm CMOS RF technology

Millimeter-wave pads based on a 65nm CMOS technology from STMicroelectronics have been designed and measured. A pad was optimized to minimize losses caused by a ground shield and by the conductive substrate. Modelling techniques and special cares to design a millimeter pad with a minimum of effects are highlighted. The goal is to integrate this pad in active devices such as a power amplifier (PA) or a low noise amplifier (LNA). The frequency response shows that the intrinsic capacitance of an optimum pad does not exceed 17fF at 60GHz. The aimed application is the unlicensed band around 60GHz suitable for Wireless Personal Area Network application (WPAN).

Optimization of 65nm CMOS passive devices to design a 16 dBm-P sat 60 GHz power amplifier

The optimization of passive devices is performed to contribute to the design of a linear 60 GHz Power Amplifier (PA). The difficulty in this design consists in the use of thin digital 7 metal layers (1P7M) Back End of Line (BEOL) and Low Power (LP) transistors dedicated for pure digital applications. In this context, compact inductors and Transmission lines (T-lines) are analyzed, measured and compared at millimeter-Wave (mmW) frequencies. Moreover, a technique of Common Mode Rejection Ration (CMRR) improvement applied for baluns is presented and validated with measurements. A Parallel PA that combines 8 high-efficiency unit power cells is designed using 65nm CMOS technology from STMicroelectronics. The experimental results show a saturated output power (Psat) of 16 dBm with a 14 dBm 1dB-output compression point (OCP1dB).

Optimized power combining technique to design a 20dB gain, 13.5dBm OCP1 60GHz power amplifier using 65nm CMOS technology

Millimeter-wave Distributed Active Transformer (DAT), baluns and zero degree 1-4 splitter have been optimized to design a 60 GHz parallel Power Amplifier (PA). The implementation is based on a thin digital 7 metal layers (1P7M) Back End of Line (BEOL) and Low Power (LP) transistors in 65 nm CMOS technology from STMicroelectronics. A lumped model based analysis is presented to compare pure voltage and mixed voltage and current combining techniques. Simulated and measured results are reported. At 61 GHz, the PA achieves a peak power gain of 20 dB with a 13.5 dBm 1dB-output compression point (OCP1dB), 15.6 dBm output power and a Power Added Efficiency (PAE) of 6.6% from a 1.2 V supply. To the authors knowledge, these results represent the highest linear output power and gain performances among PAs using the same technology.

Accurate active device characterization for a 60GHz 65nm-CMOS Power Amplifier realization

A fully integrated Power Amplifier (PA) is fabricated for the 60GHz Wireless Personal Area Network (WPAN). It is based on the 65nm CMOS technology from STMicro-electronics. The PA is matched without serial transmission lines (T-Lines) to reach good performances and low die area. S-parameters and load pull measurement results are demonstrated and compared with electromagnetic simulations for the power transistor. The PA is optimized to deliver the maximum saturated output power (Psat) under class A biasing. The PA offers a Psat of 8.2dBm, an Output Compression Point (OCP1) of 5dBm and a gain of 5.7dB. The die area is 0.29mm2 with pads.

A 0.8–11GHz 0.15μm pHEMT reconfigurable low power consumption distributed low noise amplifier for wireless home networks

A design methodology of reconfigurable distributed low noise amplifier (RDLNA) dedicated for wireless home communications operating from 0.8GHz to 11GHz is presented in this paper. This RDLNA is suitable to operate in two different operation modes: low power consumption mode and high performance mode. The used technology is 0.15μm InGaAs Active Layer pHEMT Process provided by TRIQUINT. The circuit is composed of six unit gain cells. Each cell is mounted in cascode topology. The design and the simulation results are detailed and commented. In low power consumption mode, the RDLNA has a gain of 14.0±0.3dB a noise figure (NF) of 2.4dB on average and a power consumption of 15.4mW (1.0V). In high performance mode, it demonstrates a gain of 19.8 ± 0.2dB, a NF of 1.7dB on average and a power consumption of 94.0mW(2.0V).

A compact wideband high power amplifier in GaN technology with 47% peak PAE

This article presents a 4-6GHz power amplifier in a 0.25μm GaN integrated technology from UMS foundry. Two unit power cells are combined to increase output power. A new power combiner based on a stacked balun is presented. It has the advantage of occupying a much smaller area than a conventional one. The measured circuit exhibits a peak output power of 37 dBm together with a peak PAE of 47% at 4GHz.

Characterization methodology of a millimeter-wave 65nm CMOS PA dedicated to 60GHz WPAN standard

A millimeter-wave PA (Power Amplifier) based on a 65nm CMOS technology from STMicroelectronics has been designed. It is optimized to deliver the maximum OCP1 (Output Compression Point) equal to 12dBm. The targeted feature is the unlicensed band around 60GHz suitable for Wireless Personal Area Network application (WPAN). Considering that constraints, one-tone simulations are not sufficient to characterize the linearity performances of the PA in its real conditions of use. Consequently, the high frequency memory effect is firstly highlighted by performing two-tone simulations. Linearity figures of merit are discussed applying an OFDM (Orthogonal Frequency Devising Multiplexing) modulated signal. The PA offers an ACPR of 35dB, an EVM of 20%and compresses at 9dBm.