Nicolas Mauran

Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology

A thorough analysis of the physical mechanisms involved in a vertical grounded-base n-p-n bipolar transistor (VGBNPN) under electrostatic discharge (ESD) stress is first carried out by using two-dimensional (2-D) device simulation, transmission line pulse measurement (TLP) and photoemission experiments. This analysis is used to account for the unexpected low value of the VGBNPN snapback holding voltage under TLP stress. A compact model based on a new avalanche formulation resulting from the exact resolution of the ionization integral is therefore proposed.

ESD failure signature in capacitive RF MEMS switches.

RF MEMS are commonly known as electrostatic devices using high electric field for their actuation. They can be exposed to transient voltages in any environment, and are very sensitive. According to this point of view, it is necessary to understand and analyze the degradations and failure criteria that can make them useless or reduce their lifetime. This paper deals with the investigation of ESD failure signature in capacitive RF MEMS. ESD experiments were carried out using a transmission line pulsing technique. It has been observed that electrical discharges give rise to sparks or electrical arcing and induced DC parameter shift, which can directly lead to changes in RF metrics. The contact-less dielectric charging effects of ESD pulses have been reported in this paper. It has been found that induced charges are predominant compared to injected ones through the trend of slope of the shift in the voltage corresponding to the minimum of capacitance.

Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency

In this paper, we show how latch-up guard rings, surrounding electrostatic discharges (ESD) protection devices, can reduce the overall performance of the ESD protection scheme. This issue is addressed by TCAD simulation and experimental results. Design guidelines to cope with this problem are proposed.

Analysis and compact modeling of a vertical grounded-base NPN bipolar transistor used as an ESD protection in a smart power technology

A thorough analysis of the physical mechanisms involved in a vertical grounded-base NPN bipolar transistor (VGBNPN) under ESD stress is first carried out by 2D-device simulation, square pulse measurements (TLP) and photoemission experiments. As a result, we propose a compact model using a new physics-based avalanche formulation. This allows reproduction of the unexpected low value of the VGBNPN snapback holding voltage under TLP stress.

Characterization and modeling methodology for IC’s ESD susceptibility at system level using VF-TLP tester

This paper presents various injection methods aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. A very fast transmission line pulsing (VF-TLP) tester is used to inject a disturbance into an IC under operation. A system failure criterion is chosen and a critical stress level is extracted. A modeling methodology is also developed to precisely describe each part of the set up and provide a complete model that describes the IC response to ESD indirect effects.

An Accelerated Stress Test Method for Electrostatically Driven MEMS Devices

This paper addresses an innovative solution to develop a circuit to perform accelerated stress tests of capacitive microelectromechanical-system (MEMS) switches and shows the use of instruments and equipment to monitor physical aging phenomena. A dedicated test circuit was designed and fabricated in order to meet the need for accelerated techniques for those structures. It integrated an in-house miniaturized circuit connected to additional test equipment (e.g., oscilloscopes and capacitance meters) that enabled the reliability characterization of capacitive switches. The accelerated stress test (AST) circuit generated an electrostatic-discharge-like impulse that stressed the device. This setup allowed the simultaneous measurement of the current and voltage waveforms, and the capacitance variation of the device under test after each stress. The results obtained using the miniature AST circuit were discussed and were correlated with results obtained using a commercial human-body-model tester as well as data from a cycling benchmark. The scope of this paper encompasses the theory, methodology, and practice of measurement; the development of a testing miniaturized board; and the analysis and representation of the information obtained from a set of measurements. As a result, it may contribute to the scientific and technical standards in the field of instrumentation and measurement of electrostactically actuated devices having insulating layers.

On-chip measurement to analyze failure mechanisms of ICs under system level ESD stress

Electro Static Discharge (ESD) is one of the major causes of electronic system failures. Reliability of ICs within the applications is strongly related to the on-chip propagated waveform of the ESD stress on the power supplies, the substrate and through the protections. This paper presents an on-chip oscilloscope developed for in-situ measurement of real ESD event in 65 nm CMOS technology. Dynamic measurements of overshoots, substrate fluctuation and onchip radiated fields presented in this paper are performed with 20 GHz bandwidth.

TLP-based Human Metal Model stress generator and analysis method of ESD generators

A new setup for generating a Human Metal Model compliant waveform with a TLP is described. To characterize this generator, a new analytical method has been developed, which is applicable to both TLP and HMM and demonstrates fundamental differences between those three types of generators. Results are used to correlate failure levels on active devices.

20 GHz on-chip measurement of ESD waveform for system level analysis

This paper deals with on-chip oscilloscope developed for in-situ measurement of real ESD event in 65nm CMOS technology. The measurement bandwidth of the embedded sampler is 100GHz, and 20GHz for the probes. Some measurement results during an ESD stress on an I/O structure are presented.