Nicolas Menou

Atomic Layer Deposition of Strontium Titanate Films Using Sr ( #2#1Cp ) 2 and Ti ( OMe ) 4

Strontium titanate (STO) is a promising candidate as a high-k dielectric for dynamic random access memory application. STO thin films are deposited by atomic layer deposition using Sr( t Bu 3 Cp) 2 , Ti(OMe) 4 , and H 2 O as precursors. Growth and saturation behavior of STO and binary oxides are evaluated by ellipsometry thickness measurements. The precursor pulse ratio controls the amount of Sr and Ti incorporated in STO films. Stoichiometric SrTiO 3 is characterized by the lowest crystallization temperature and largest refractive index, density, and dielectric constant. An excess of Ti or Sr results in an increase in the crystallization onset temperature and contraction or expansion of the cubic cell constant of perovskite SrTiO 3 . Incorporation of more Sr in STO reduces the leakage current density but also increases the capacitance-equivalent thickness.

Composition influence on the physical and electrical properties of SrxTi1−xOy-based metal-insulator-metal capacitors prepared by atomic layer deposition using TiN bottom electrodes

In this work, the physical and electrical properties of SrxTi1−xOy (STO)-based metal-insulator-metal capacitors (MIMcaps) with various compositions are studied in detail. While most recent studies on STO were done on noblelike metal electrodes (Ru, Pt), this work focuses on a low temperature (250 °C) atomic layer deposition (ALD) process, using an alternative precursor set and carefully optimized processing conditions, enabling the use of low-cost, manufacturable-friendly TiN electrodes. Physical analyses show that the film crystallization temperature, its texture and morphology strongly depends on the Sr/Ti ratio. Such physical variations have a direct impact on the electric properties of SrxTi1−xOy based capacitors. It is found that Sr-enrichment result in a monotonous decrease in the dielectric constant and leakage current as predicted by ab initio calculations. The intercept of the EOT vs physical thickness plot further indicates that increasing the Sr-content at the film interface with the bottom TiN...

A highly reliable 3-D integrated SBT ferroelectric capacitor enabling FeRAM scaling

Ferroelectric random access memories (FeRAMs) combine very attractive properties such as low-voltage operation, fast write and nonvolatility. However, unlike Flash memories, FeRAMs are difficult to scale along with the CMOS technology roadmap, mainly because of the decrease of available signal with decreasing cell area. One solution for further scaling is to integrate three-dimensional (3-D) FeCAPs. In this paper, we have integrated a 3-D FeCAP structure in a 0.35-/spl mu/m CMOS technology whereby the effective area of <1 /spl mu/m/sup 2/ single FeCAPs is increased by a factor of almost two. We show that, after optimization of the metal-organic chemical vapor deposition (MOCVD) deposition and post-anneal steps of the Sr/sub 0.8/Bi/sub 2.2/Ta/sub 2/O/sub 9/ (SBT) layer, the sidewall SBT contributes to the polarization Pr, resulting in higher Pr values for 0.81-/spl mu/m/sup 2/ three-dimensional (3-D) capacitors (2Pr/spl ap/15 /spl mu/C/cm/sup 2/) than for 1000 /spl mu/m/sup 2/ 2-D capacitors (2Pr/spl ap/10 /spl mu/C/cm/sup 2/). Moreover, these 3-D capacitors are observed to be fatigue-free and imprint-free up to 10/sup 11/ cycles (5-V square pulses), and extrapolations of retention tests indicate less than 10% Pr loss after ten years at 85/spl deg/C, which shows that sidewall SBT retains the same excellent reliability properties as 2-D capacitors. We demonstrate in this paper that the negative signal-scaling trend can be halted using 3-D FeCAPs. To our knowledge, this paper is the first report on electrical and reliability properties of integrated 3-D FeCAPs, and is a starting point for future development work on densely scaled FeRAMs.

Alternative high-k dielectrics for semiconductor applications

Although the next generation high-k gate dielectrics has been defined for the 45nm complementary metal oxide semiconductor technology node, threshold voltage control and equivalent oxide thickness (EOT) scaling remain concerns for future devices. Therefore, the authors explored the effect of incorporating dysprosium in the gate stack. Results suggest that improved EOT-leakage scaling is possible by adding Dy to the interfacial SiO2 layer in a 1:1 ratio or by adding 10% Dy to bulk HfO2. The deposition of a 1nm Dy2O3 cap layer lowered the threshold voltage by ∼250mV. In addition, for future dynamic random access memory capacitor applications, dielectrics with e of 50–130 are projected by the International Technology Roadmap for Semiconductors, unachievable with standard high-k dielectrics. Theoretical modeling can help direct the experimental work needed for extensive screening of alternative dielectrics. Moreover, materials such as perovskites only exhibit a sufficiently high-k value when properly crystall...

Impact of (111)-oriented SrRuO3/Pt tailored electrode for highly reproducible preparation of metal organic chemical vapour deposited Pb(Zr,Ti)O3 films for high density ferroelectric random access memory applications

In the present paper we report a comparative study of the structural, morphologic, and electric properties of Pb(Zr,Ti)O3 films, deposited by pulsed metal-organic chemical vapour deposition (MOCVD), on different (111)-oriented bottom-electrode stacks (SrRuO3/Pt, Pt, and Ir substrates). The Pb input ratio in the MOCVD chamber was systematically modified for each deposition run to obtain PZT films with various compositions within the Pb process window. Our results clearly demonstrate that only PZT films deposited on SrRuO3 show high quality and reproducible properties throughout the process window, i.e., high (111) texture, low roughness (<5 nm), high Pr (~40 µC/cm2), low Vc (<1 V), as well as a relatively low leakage current (~10-5 A/cm2 at 1.5 V). This study provides further evidence that SrRuO3/Pt substrates are good candidates for integration in next-generation high-density ferroelectric random access memories (FeRAM).

High Efficiency Silver-Free Heterojunction Silicon Solar Cell

In this work, we present the results of the replacement of silver screen printing on heterojunction crystalline silicon (c-Si) solar cells with a copper metallization scheme that has the potential to reduce the manufacturing cost while improving their performance. We report for the first time silver-free heterojunction c-Si solar cells on 6-in. wafers. The conversion efficiency reached is a record 22.1% for c-Si technology for this wafer size (Voc = 729 mV, Jsc = 38.3 mA/cm2, FF= 79.1%). The total power generated is more than 5 W for 1-sun illumination, which is a world record. Heat-damp reliability tests show comparable performance for mini-modules fabricated with copper metalized as for conventional silver screen printed heterojunction c-Si solar cells.

Impact of thermal treatment upon morphology and crystallinity of strontium titanate films deposited by atomic layer deposition

Strontium titanate (STO) is a dielectric with a cubic perovskite type structure and of increasing interest for microelectronics, especially in the metal-insulator-metal (MIM) capacitors due to its high dielectric constant. The dielectric constant of the STO films and consequently the performance of the MIM capacitors appear to be strongly influenced by the process conditions. In this work the authors report on the influence of various thermal treatments upon the crystallinity and morphology of strontium titanate crystals. The influence of spike, laser, or rapid thermal anneals on the morphology with respect to grain size and topography of the crystalline stoichiometric STO films is studied. Also, the use of a stack containing a Sr-rich STO (62% Sr) bottom seed layer and a stoichiometric STO top layer in combination with a thermal treatment was found to affect the microstructure of the STO film. A comparison of the electrical properties for various thermal treatments has been made.

High-k Dielectrics and Metal Gates for Future Generation Memory Devices

The requirements and development of high-k dielectric films for application in storage cells of future generation flash and Dynamic Random Access Memory (DRAM) devices are reviewed. Dielectrics with k-value in the 9-30 range are studied as insulators between charge storage layers and control gates in flash devices. For this application, large band gaps (> 6 eV) and band offsets are required, as well as low trap densities. Materials studied include aluminates and scandates. For DRAM metal-insulator-metal (MIM) capacitors, aggressive scaling of the equivalent oxide thickness (with targets down to 0.3 nm) drives the research towards dielectrics with k-values > 50. Due to the high aspect ratio of MIMCap structures, highly conformal deposition techniques are needed, triggering a substantial effort to develop Atomic Layer Deposition (ALD) processes for the deposition of metal gates and high-k dielectrics. Materials studied include Sr and Ba-based perovskites, with SrTiO3 as one of the most promising candidates, as well as tantalates, titanates and niobates.

Growth and Material Characterization of Hafnium Titanates Deposited by Atomic Layer Deposition

Hafnium titanate (HTO) films were deposited within a large Hf-Ti compositional range by atomic layer deposition using HfCl4/TiCl4/H2O precursors. The Hf content of the layers is well controlled by the precursor pulse ratio, as indicated by Rutherford backscattering. The saturation conditions of ternary HTOs are different compared to those of the binary oxides, First-principles simulation confirmed the enhancement of the Hf precursor reactivity in the presence of Ti-OH. Growth curves of HTOs showed a good linearity with the number of reaction cycles. A linear correlation between density, quantified by X-ray reflectometry, and composition was observed. X-ray diffraction indicated that the as-deposited films are amorphous up to 500-700 degrees C, depending on the Hf/Ti ratio. The orthorhombic HfTiO4 diffraction lines in the samples (30-64% Hf) annealed at 850 degrees C were observed. For a Hf content higher than 82%, a monoclinic HfO2-Iike structure was reported. The dielectric constant and leakage current depend on the Ti content, the film crystallinity, and the anneal atmosphere. The posideposition anneal in O-2, is found to have a drastic effect in leakage Current density reduction and could be a key for further improvements of HTO electrical properties.

0.5 nm EOT low leakage ALD SrTiO 3 on TiN MIM capacitors for DRAM applications

We demonstrate for the first time record low Leakage-EOT (3.5 times 10-7 A/cm2 at 1V, EOT=0.49 nm) MIM capacitors fabricated using a low temperature (250degC) ALD SrTiO3 (STO) deposition process on ALD TiN bottom electrode. While most previous work on STO used deposition techniques not compatible with high aspect ratio DRAM applications, recent work on ALD STO showed promise on noble-like metal electrodes (Ru, Pt) [1,2]. In this work, a low temperature ALD process with alternative precursor set and carefully optimized deposition and processing conditions enables the use of low-cost, manufacturable-friendly TiN electrode MIMcaps for future DRAM nodes. Composition (Sr-rich) and process optimization allowed minimization of interfacial EOT penalties and leakage reduction by decreasing the density of leakier STO grains.