Niklas Lotze

A 62 mV 0.13

Sub-threshold circuits have recently gained attention mainly due to the possibility of operating at the minimum energy per operation point [1]. There are applications where a supply voltage reduction below this point is advantageous though, even at the cost of increasing active energy per operation. Always-on circuits, e.g. wake-up circuitry for chips sleeping at ultra-low supply voltages, reduce power consumption with decreasing supply. Furthermore, energy-harvesting applications are often limited by the very low output voltages of the harvesting devices, thus the minimum VDD of the electronic circuits dictates when active operation can start (e.g. thermoelectric harvesters [2]).

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This work presents a formulation of the FIR filter problem with sum of power-of-two (POT) coefficients as a mixed integer linear problem and solves it heuristically. The optimization problem is formulated to minimize the number of nonzero bits in each coefficient without violating the filter specifications within the pass and stop bands. A novel fast and efficient local search optimization algorithm for the filter coefficients is proposed. The algorithm called POTx does not use a tree structure in contrast to conventional MILP algorithms and offers fast computation because of a presorted search space, a monotonic dedicated search space, and the use of abort conditions. The proposed approach achieves comparable reductions to nonheuristic approaches because of a hybrid allocation scheme and multiple optimization iterations. The usefulness of the proposed algorithm for low power design of FIR filters is shown through the evaluation of several benchmark filters.

m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic

The design of sub-threshold circuits is especially challenging due to the massive impact of process variations. These variabilities also heavily affect circuit timing, a problem only considered concerning combinational gates so far. In this paper the effects of process variations on flip-flop timing at sub-threshold voltages are analyzed based on extensive monte-carlo simulations. The results show that the usual timing-optimal definition of timing parameters needs to be replaced by a reliability-driven approach. The model is validated for sub- and near-threshold supply voltages and an approach for energy-optimal sizing is presented.

A Novel Hybrid Monotonic Local Search Algorithm for FIR Filter Coefficients Optimization

This paper investigates self-timed asynchronous design techniques for subthreshold digital circuits. In this voltage range extremely high voltage-dependent delay uncertainties arise which make the use of synchronous circuits rather inefficient or their reliability doubtful. Delay-line controlled circuits face these difficulties with self-timed operation with the disadvantage of necessary timing margins for proper operation. In this paper we discuss these necessary timing overheads and present our approach to their analysis and reduction to a minimum value by the use of circuit techniques allowing completion detection. Transistor-level simulation results for an entirely delay-adaptable counter under variable supply down to 200 mV are presented. Additionally an analytical comparison and simulation of timing and energy consumption of more complex subthreshold asynchronous circuits is shown. The outcome is that a combination of delay-line based circuits with circuits using completion detection is promising for applications where the supply voltages are at extremely low levels.

Variability of flip-flop timing at sub-threshold voltages

This brief proposes a new approach to utilizing positive-offset representation for sign-extension avoidance in shift-and-add implementation of a finite-impulse response filter. Affine arithmetic is used to model the excess offsets in order to curtail the word-length (WL) expansion problem. Tighter probabilistically justified WL bounds are determined to enable further offset to be removed from each tap. The approach is applicable even after the redundant adders in the multiplier block of the filter have been minimized. Our simulation results show an average power reduction of about 19% over and above the savings achieved by sharing of adders in multiple constant multiplication.

A Study on self-timed asynchronous subthreshold logic

This paper introduces a state-of-the-art design of a high speed sigma delta digital to analog converter (DAC), which can be integrated into a system-on-a-chip (SOC) for different communication transceivers. The operation speed in the digital circuit is very important for accomplishing the performance which can satisfy different communication protocol specifications. This paper therefore addresses this problem by using a parallel structure for radio frequency modulation at system level and by using redundancy coding for speed improvement at register transfer level. Due to the flexibility of the sigma delta structure, the designs can trade off between bandwidth and signal-to-noise ratio (SNR) to adapt to different digital communication protocol specifications. A 4th order structure can e.g. achieve 6.5 MHz single-side bandwidth (SBW) with 99 dB SNR at base band; or it can achieve 26 MHz double-side bandwidth with 73 dB SNR. Moreover, if latches are used, the sampling frequency can reach 1.4 GHz in a 5th order 2bit structure implemented in a 0.13 mum ASIC, which can achieve 29 MHZ SBW with 81 dB SNR. These implementations occupy very little area as demonstrated in the data obtained from synthesis in a 0.13 mum CMOS standard cell library. These sigma delta structures therefore can be integrated in a SOC for different digital communication transceivers effectively.

Sign-Extension Avoidance and Word-Length Optimization by Positive-Offset Representation for FIR Filter Design

Despite an increasing interest in digital subthreshold circuits little research has been dedicated to timing modeling in this voltage domain so far. Especially high timing variabilities makes proper modeling necessary to allow for the prediction of timing behavior and timing yield on the path towards design automation. This paper first deals with gate timing characterization at sub-threshold voltages and a characterization waveform well resembling the actual transistor-level waveforms in this voltage domain is proposed. The error made in this abstraction step is identified and shown to be typically below 3%. Secondly, the modeling of timing variability is considered and the high correlation between gate delays due to slope propagation combined with strong non-linearities in the delay-slope dependencies are pointed out as modeling challenges. A path-based logic-level Monte-Carlo technique, already magnitudes faster than transistor-level simulation, is applied and shown to match transistor-level Monte-Carlo simulation results better than 3% in mean and 7% in standard deviation values.

On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip

A novel method for approximating filter coefficients to signed-power-of-two terms is proposed yielding a significant reduction in complexity and power consumption. A Matlab toolbox named MSD-Toolbox (multi-stage decimation) was developed to design and optimize multi-stage decimation filters. The proposed design methodology was used to design an example decimation filter, which was synthesized in 0.13 mum CMOS technology. The power consumption of the synthesized structure was analyzed. A reduction in power consumption of about 20% has been achieved for a 3-bit, second order lowpass sigma delta ADC decimation filter stage when compared with the conventional structure. For the well known quadratic polynomial objective function of FIR filters a novel subject constraint and limited signed-power-of-two space has been introduced.

Timing modeling for digital sub-threshold circuits

This paper presents the implementation and power analysis of an efficient decimator architecture for cascaded sigma-delta (SigmaDelta) modulators. The recombination logic for cascaded modulators in general and a gain error correction for continuous time (CT) modulators are integrated into the first decimation stage. An appropriate filter topology is derived and synthesized in a 0.18 mum CMOS technology using synopsys design compiler. The power consumption of the various blocks is analyzed using stimuli of a SOFO SigmaDelta-modulator and synopsys primepower. A comparison of the proposed architecture to a conventional implementation shows a remarkable reduction of power consumption by a factor of 4.

Optimized scheme for power-of-two coefficient approximation for low power decimation filters in sigma delta ADCs

Energy harvesting micro-generators provide alternative sources of energy for many technical and personal applications. Since the power delivered by such miniaturized devices is limited they need to be optimized and adapted to the application. The associated electronics not only has to operate at very low voltages and use little power it also needs to be adaptive to the fluctuating harvesting conditions. A joint development and optimization of transducer and electronics is essential for improved efficiency.