Samir Parikh

A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS

Standards such as OIF CEI-25G, CEI-28G and 32G-FC require transceivers operating at high data rates over imperfect channels. Equalizers are used to cancel the inter-symbol interference (ISI) caused by frequency-dependent channel losses such as skin effect and dielectric loss. The primary objective of an equalizer is to compensate for high-frequency loss, which often exceeds 30dB at fs/2. However, due to the skin effect in a PCB stripline, which starts at 10MHz or lower, we also need to compensate for a small amount of loss at low frequency (e.g., 500MHz). Figure 2.1.1 shows simulated responses of a backplane channel (42.6dB loss at fs/2 for 32Gb/s) with conventional high-frequency equalizers only (4-tap feed-forward equalizer (FFE), 1st-order continuous-time linear equalizer (CTLE) with a dominant pole at fs/4, and 1-tap DFE) and with additional low-frequency equalization. Conventional equalizers cannot compensate for the small amount of low-frequency loss because the slope of the low-frequency loss is too gentle (<;3dB/dec). The FFE and CTLE do not have a pole in the low frequency region and hence have only a steep slope of 20dB/dec above their zero. The DFE cancels only short-term ISI. Effects of such low-frequency loss have often been overlooked or neglected, because 1) the loss is small (2 to 3dB), 2) when plotted using the linear frequency axis which is commonly used to show frequency dependence of skin effect and dielectric loss, the low-frequency loss is degenerated at DC and hardly visible (Fig. 2.1.1a), and 3) the long ISI tail of the channel pulse response seems well cancelled at first glance by conventional equalizers only (Fig. 2.1.1b). However, the uncompensated low-frequency loss causes non-negligible long-term residual ISI, because the integral of the residual ISI magnitude keeps going up for several hundred UI. As shown by the eye diagrams in the inset of Fig. 2.1.1(b), the residual long-term ISI results in 0.42UI data-dependent Jitter (DDJ) that is difficult to reduce further by enhancing FFE/CTLE/DFE, but can be reduced to 0.21UI by adding a low-frequency equalizer (LFEQ). Savoj et al. also recently reported long-tail cancellation [2].

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS

This paper presents a 40 Gb/s serializer IC in 65 nm bulk CMOS technology. The IC has an SFI5.2-compliant 10 Gb/s input interface and supports two different output modes, single 40 Gb/s for OC-768 VSR and dual 20 Gb/s for DQPSK. The IC is evaluated on a PCB and error-free operation is confirmed. The chip consumes 1.8 W for the 40 G mode, and 1.6 W for the 20 G mode from 1.2 V and 3.3 V power supplies.

A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.

A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel

In multi-Gb/s wireline communications, equalizers are used to compensate for channel-induced signal distortion in order to stretch the maximum distance of transmission. Both amplitude and phase can be distorted in a channel. Amplitude distortion is a frequency-dependent attenuation due to skin effect and dielectric loss, causing inter-symbol-interference (ISI). A transmitter (TX) discrete-time pre-emphasis (PE) filter, a receiver (RX) continuous-time Linear Equalizer (LE), and an RX Decision-Feedback Equalizer (DFE) are generally used to cancel ISI. At 10Gb/s or higher data rate, equalizers for up to 33 to 39dB Nyquist loss and up to 20 to 25dB adapted loss range were reported [1–3]. On the other hand, how to compensate phase distortion is not clearly understood in practical circuit design. Theoretically, if a channel has minimum-phase-likecharacteristics, phase distortion is automatically co-equalized with amplitude distortion by a minimum-phase equalizer [4]. While this is the case for high-speed cables [5], it is not for PCB traces, because a non-minimum-phase equalizer, e.g., a PE with a pre-cursor tap, produces lower BER over a high-loss PCB channel than a minimum-phase equalizer, e.g., a PE without a pre-cursor tap. Thus the IEEE 10Gb Ethernet standard for backplanes adopted 3-tap PE with a precursor tap [6]. However, adaptive phase equalization in hardware has not been reported in the literature.

A DC-46Gb/s 2:1 multiplexer and source-series terminated driver in 20nm CMOS technology

We present a 46Gb/s 2:1 multiplexer and a source series terminated full rate driver for high speed chip-to-chip communications. The multiplexer and the driver are implemented using the pseudo-differential static CMOS circuit. Transmitter driver uses the push-pull structure to produce a VDD peak-to-peak differential voltage swing. The circuit uses no current mode logic gates or large on-chip passive devices aside from series-connected on-chip resistor and the T-coil used to minimize the return loss. We confirmed the total jitter of about 7ps at 46Gb/s and eye opening of 0.605UI up to 50 Gb/s on the test circuit fabricated in 20nm CMOS technology. Measured power consumption is 38.7mW at 46Gb/s (0.84pJ/b power efficiency).