Nivard Aymerich

Variability Mitigation Mechanisms in Scaled 3T1D-DRAM Memories to 22 nm and Beyond

It has been stated that 3T1D-DRAM cell is a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by variability. In this paper, it is shown that the 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation when they are scaled to nodes smaller than 22 nm. Furthermore, we present some strategies to mitigate the cell variability. Moreover, while scaling down capacitorless DRAM cells is a challenging trend, we also show how the scaling drawbacks can be compensated through the following: 1) the channel strain of the cell devices and 2) the proposal of new strategies to further enhance the memory cell behavior.

Adaptive Fault-Tolerant Architecture for Unreliable Technologies With Heterogeneous Variability

This paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We propose an adaptive structure that is able to cope with nonhomogeneous variability and time-varying effects like degradation and external aggressions, which are expected to be key limiting factors in future technologies. First, we consider static heterogeneity of the input variability levels and derive a methodology to determine the weight values that maximize the reliability of the averaging system. The implementation of these optimal weights in the AVG gives place to the unbalanced AVG structure (U-AVG). Second, we take into consideration that circuits are exposed to time-dependent aggression factors, which can induce significant changes on the levels of variability, and introduce the adaptive AVG structure (AD-AVG). It embeds a learning mechanism based on a variability monitor that allows for the on-line input weight adaptation such that the actual weight configuration properly reflects the aging status. To evaluate the potential implications of our proposal, we compare the conventional AVG architecture with the unbalanced (U-AVG) and the adaptive (AD-AVG) approaches in terms of reliability and redundancy overhead by means of Monte Carlo simulations. Our results indicate that when AVG and U-AVG are exposed to the same static heterogeneous variability, U-AVG requires 4 less redundancy for the same reliability target. Subsequently, we include temporal variation of input drifts in the simulations to reproduce the effects of aging and external aggressions and compare the AVG structures. Our experiments suggest that AD-AVG always provides the maximum reliability and the highest tolerance against degradation. We also analyze the impact of nonideal variability monitor on the effectiveness of the AD-AVG behavior. Finally, specific reconfigurable hardware based on resistive switching crossbar structures is proposed for the implementation of AD-AVG.

Impact of FinFET and III–V/Ge Technology on Logic and Memory Cell Behavior

In this paper, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFETs, and III-V MOSFETs), and subjected to different reliability scenarios (variability and soft errors). FinFET-based circuits show the highest robustness against variability and soft error environments.

New reliability mechanisms in memory design for sub-22nm technologies

The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells, and what kind of circuit solution would be required to maintain the current yield level. Later, we discuss the impact of errors at the system level, and different approaches at system level to adapt the heterogeneous systems to users requirements.

Impact of FinFET Technology Introduction in the 3T1D-DRAM Memory Cell

In this paper, the 3T1D-DRAM cell based on FinFET devices is studied as an alternative to the bulk one. We observe an improvement in its behavior when IG and SG FinFETs are properly mixed, since together they provide a relevant increase in the memory circuit retention time. Moreover, our FinFET cell shows larger variability robustness, better performance at low supply voltage, and higher tolerance to elevated temperatures.

Systematic and random variability analysis of two different 6T-SRAM layout topologies

This paper studies the device variability influence on 6T-SRAM cells in a function of the regularity level of their layout. Systematic and random variations have been analyzed when these memory circuits are implemented on a 45nm technology node. The NBTI aging relevance on these cells has been also studied for two layout topologies and SNM has been seen as the parameter that suffers the highest impact with respect to cell aging and variability.

Degradation Stochastic Resonance (DSR) in AD-AVG architectures

This paper introduces for the first time the Degradation Stochastic Resonance (DRS) effect observed in the Adaptive Averaging (AD-AVG) architecture. This phenomenon, closely related to the well-known Suprathreshold Stochastic Resonance (SSR), influences the AD-AVG behavior for specific noise conditions and causes a yield improving effect over the degradation in time. In this article we analyze this counter-intuitive effect and explain the most relevant features. We observe, for example, that the yield of 20-input AD-AVG with 0.4 V of noise in the variability monitor increases from 0.93 to 0.97 after particular amounts of degradation.

Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells

Memory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure could exhibit serious limitations in future CMOS technologies due to the instability caused by transistor mismatching as well as for leakage consumption reasons. For L1 data caches the new cell 3T1D DRAM is considered a potential candidate to substitute 6T SRAMs. We first evaluate the impact of the positive bias temperature instability, PBTI, on access and retention times of the 3T1D memory cell implemented in 45, 22 and 16nm technology. Then, we consider all sources of variations and the effect of the degradation caused by the aging of the devices and estimate the yield at system level.

Suitability of the FinFET 3T1D Cell Beyond 10 nm

The performance of the 3T1D-DRAM cell beyond 10-nm technology node is investigated when the memory cell is based on nonplanar multigate devices, i.e., FinFETs. Moreover, for completeness, the cell is analyzed in both SOI and bulk-based FinFETs. While relevant process variation robustness is observed in SOI-based FinFETs, 10× lower impact than for bulk-based ones. In order to improve the variability robustness of bulk-based FinFET cell, we propose a dual-VT strategy to enhance the dynamic cell behavior.

Reliability and Performance Tunable Architecture: The Partially Asynchronous R-Fold Modular Redundancy (pA-RMR)

The R-fold modular redundancy (RMR) is a widely known fault-tolerant architecture based on hardware redundancy. It improves the system reliability by replicating the basic computing element and combining all the results with a majority criterion. In this analytic study, we extend this conventional approach by introducing the time dimension in the RMR design. Indeed, the asynchronous nature of future nanoelectronic computing systems is taken into account by introducing the partially asynchronous RMR (pA-RMR) structure whose main feature is to detect the arrival of each input signal from the replicas based on the use of tokens. The voter behavior is modified in such a way that it sets the output result after a determined number of token arrivals. By doing this, we are adding a second degree of freedom to the RMR structure, which not only has a configurable size (R replicas), but also allows modifying the number of tokens it waits before giving an output. As a consequence of this seemingly simple change, we are able to exploit new possibilities of this redundant structure. This second degree of freedom allows choosing between system reliability and performance during operation. The number of available replicas in the pA-RMR architecture determines the maximum reliability achievable, while the voting policy allows us to adapt the structure to different design requirements and achieve the desired balance between reliability and performance.