Nobuaki Ohtsuka

A 4-Mbit CMOS EPROM

A high-density (512K-word/spl times/8-b) erasable programmable read-only memory (EPROM) has been designed and fabricated by using 0.8-/spl mu/m n-well CMOS technology. A novel chip layout and a sense-amplifier circuit produce a 120-ns access time and a 4-mA operational supply current. The interpoly dielectric, composed of a triple-layer structure, realizes a 10-/spl mu/s/byte fast programming time, in spite of scaling the programming voltage V/SUB PP/ from 12.5 V for a 1-Mb EPROM to 10.5 V for this 4-Mb EPROM. To meet the increasing demand for a one-time programmable (OTP) ROM, a circuit is implemented to monitor the access time after the assembly. A novel redundancy scheme is incorporated to reduce additional tests after the laser fuse programming. Cell size and chip size are 3.1/spl times/2.9 /spl mu/m/SUP 2/ and 5.86/spl times/14.92 mm/SUP 2/, respectively.

A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique

To meet the increasing demand for higher-density and faster EPROMs, a 16-Mb CMOS EPROM has been developed based on 0.6- mu m N-well CMOS technology. In scaled EPROMs, it is important to guarantee device reliability under high-voltage operation during programming. By employing internal programming-voltage reduction and new stress relaxation circuits, it is possible to keep an external programming voltage V/sub pp/ of 12.5 V. The device achieves a 62-ns access time with a 12-mA operating current. A sense-line equalization and data-out latching scheme, made possible by address transition detection (ATD), and a bit-line bias circuit with two types of depletion load led to the fast access time with high noise immunity. This 16-Mb EPROM has pin compatibility with a standard 16-Mb mask-programmable ROM (MROM) and is operative in either word-wide or byte-wide READ mode. Cell size and chip size are 2.2 mu m*1.75 mu m and 7.18 mm*17.39 mm, respectively. >

A 3.3 V-only 16 Mb flash memory with row-decoding scheme

A 3.3 V only 16 M flash memory with a row decoding scheme is fabricated in 0.4 /spl mu/m double-well double-metal CMOS. Negative-gate-biased erase enables 3.3 V-only operation, and a double-word-line structure with second aluminum minimizes word-line delay. Row redundancy with self-convergence improves yield. Quasi-differential sensing with address transition detection gives fast random access.

A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design

In a VLSI memory, noise generated by its own operation is a serious problem. The noise disturbs data sensing, especially in EPROMs which have a single-ended sensing scheme. To develop high-density and high-speed EPROMs, it is necessary to solve the noise problems. Incorrect EPROM functions due to the noise are discussed. High-noise-immunity circuit techniques for stable data sensing and high-speed access time are proposed. These are divided bit-line layout, reference line with dummy bit lines, and a chip-enable transition detector. Using these circuit techniques and 0.8- mu m n-well CMOS technology, a 512 K*8-b CMOS EPROM was developed. A 68-ns access time was achieved. The die size is 5.62 mm*15.30 mm, and it is assembled in a 600-mil cerdip package. >

A 120ns 4Mb CMOS EPROM

A 512K×8b EPROM fabricated in 0.8μm, CMOS with a cell size of 9μm2and a chip size of 5.9×14.9mm2will be reported. The device programs at a rate of 10μs per byte, reads with an access time of 120ns and draws 10mA of active current.