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Dive into the research topics where Naoto Tomita is active.

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Featured researches published by Naoto Tomita.


IEEE Journal of Solid-state Circuits | 1991

A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique

Naoto Tomita; Nobuaki Ohtsuka; Junichi Miyamoto; Kenichi Imamiya; Y. Iyama; S. Mori; Y. Ohsima; N. Arai; Y. Kaneko; E. Sakagami; K. Yoshikawa; Sumio Tanaka

To meet the increasing demand for higher-density and faster EPROMs, a 16-Mb CMOS EPROM has been developed based on 0.6- mu m N-well CMOS technology. In scaled EPROMs, it is important to guarantee device reliability under high-voltage operation during programming. By employing internal programming-voltage reduction and new stress relaxation circuits, it is possible to keep an external programming voltage V/sub pp/ of 12.5 V. The device achieves a 62-ns access time with a 12-mA operating current. A sense-line equalization and data-out latching scheme, made possible by address transition detection (ATD), and a bit-line bias circuit with two types of depletion load led to the fast access time with high noise immunity. This 16-Mb EPROM has pin compatibility with a standard 16-Mb mask-programmable ROM (MROM) and is operative in either word-wide or byte-wide READ mode. Cell size and chip size are 2.2 mu m*1.75 mu m and 7.18 mm*17.39 mm, respectively. >


international solid-state circuits conference | 1996

A 3.3 V-only 16 Mb flash memory with row-decoding scheme

Shigeru Atsumi; Akira Umezawa; Masao Kuriyama; Hironori Banba; Nobuaki Ohtsuka; Naoto Tomita; Y. Iyama; Takeshi Miyaba; R. Sudoh; E. Kamiya; M. Tanimoto; Y. Hiura; Y. Araki; E. Sakagami; N. Arai; S. Mori

A 3.3 V only 16 M flash memory with a row decoding scheme is fabricated in 0.4 /spl mu/m double-well double-metal CMOS. Negative-gate-biased erase enables 3.3 V-only operation, and a double-word-line structure with second aluminum minimizes word-line delay. Row redundancy with self-convergence improves yield. Quasi-differential sensing with address transition detection gives fast random access.


vlsi test symposium | 1992

Optimum redundancy design for new-generation EPROMs based on yield analysis of previous generation

Keniti Imamiya; Junichi Miyamoto; N. Ohtuska; Naoto Tomita; Yumiko Iyama

Failure modes of 4 Mbit EPROMs have been analyzed, and the model to formulate them is proposed. The redundancy scheme of a 16 Mbit EPROM was optimized by the model in consideration of area penalty. In applying the 4 Mbit data to 16 Mbit EPROM, fabrication line improvement was taken into account. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction. The 16 Mbit EPROM has 2 rows*8 blocks redundancy, and the redundancy gives the highest yield in the time when the mass production begins.<<ETX>>


Archive | 1999

Semiconductor storage device with automatic write/erase function

Hidetoshi Saito; Hideo Kato; Naoto Tomita; Tokumasa Hara


Archive | 1997

Potential detecting circuit which suppresses the adverse effects and eliminates dependency of detected potential on power supply potential

Naoto Tomita


international solid-state circuits conference | 1991

A 62ns 16Mb CMOS EPROM With Address Transition Detection Technique

Nobuaki Ohtsuka; Junichi Miyamoto; Kenichi Imamiya; Naoto Tomita; Y. Iyama; S. Mori; Y. Ohshima; N. Arai; Y. Kaneko; E. Salkagami; K. Yoshikawa; Sumio Tanaka


Archive | 1991

Semiconductor memory having redundant cells

Naoto Tomita; Junichi Miyamoto


Archive | 2001

Pulse generator circuit and semiconductor memory provided with the same

Naoto Tomita; Hideo Kato; Takafumi Ikeda


Archive | 1994

Semiconductor memory device having a delay circuit for controlling access time

Naoto Tomita; Imamiya Keniti; Nobuaki Ohtsuka; Junichi Miyamoto


Archive | 1999

Power source circuit device used for a semiconductor memory

Naoto Tomita

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