Nobuhiro Shimoyama

A novel semiconductor capacitive sensor for a single-chip fingerprint sensor/identifier LSI

We describe a new semiconductor capacitive sensor structure and the fabrication process for a single-chip fingerprint sensor/identifier LSI in which the sensor is stacked on a 0.5-/spl mu/m CMOS LSI. To ascertain the influence of the fabrication process and normal usage on the underlying LSI, sensor chips were subjected to an electrostatic discharge (ESD) test, mechanical stress test, and unsaturated pressure cooker test (USPCT). ESD tolerance is obtained at the value of /spl plusmn/3.0 kV. To investigate mechanical stress, we carried out a tapping test. The sensor is immune to mechanical stress under the condition of 10/sup 4/ taps with the strength of 1 MPa. A multilayer passivation film consisting SiN under polyimide film provides protection against contamination such as water. Thus, under USPCT conditions of 130/spl deg/C, 80% humidity, and 48 h, the chips were not degraded. The tests confirm that the proposed sensor has sufficient reliability for normal identification usage.

128×128 three-dimensional MEMS optical switch module with simultaneous optical path connection for optical cross-connect systems

A 128×128 three-dimensional MEMS optical switch module and a switching-control algorithm for high-speed connection and optical power stabilization are described. A prototype switch module enables the simultaneous switching of all optical paths. The insertion loss is less than 4.6 dB and is 2.3 dB on average. The switching time is less than 38 ms and is 8 ms on average. We confirmed that the maximum optical power can be obtained and optical power stabilization control is possible. The results confirm that the module is suitable for practical use in optical cross-connect systems.

Improvement of water-related hot-carrier reliability by using ECR plasma-SiO/sub 2/

Water-related hot-carrier degradation is reduced by using ECR plasma-SiO/sub 2/ as the water-blocking layer under the water-containing films such as SOG or TEOS-O/sub 3/. A water-blocking mechanism is proposed, based upon the reaction between Si-H bonds and H/sub 2/O in ECR-SiO/sub 2/ film. Hot-carrier degradation is reduced as SiH/sub 4//O/sub 2/ gas flow ratios (/spl alpha/) are increased during ECR-SiO/sub 2/ deposition. Degradation does not occur when /spl alpha//spl ges/0.69. The Si-H bond concentration in ECR-SiO/sub 2/ film increases as /spl alpha/ increases. In water-containing SOG film covered with ECR-SiO/sub 2/, the amount of petrology desorbed increases as /spl alpha/ increases, while the amount of water desorbed decreases. These results confirm that the water-blocking ability of ECR-SiO/sub 2/ is caused by water decomposition resulting from the reaction between Si-H bonds and H-O in ECR-SiO/sub 2/. >

Enhanced hot-carrier degradation due to water-related components in TEOS/O/sub 3/ oxide and water blocking with ECR-SiO/sub 2/ film

The authors point out that a TEOS/O/sub 3/-oxide layer used as an interlevel dielectric enhances hot-carrier degradation of MOSFETs due to the water-related components (water and/or silanols) contained in the layer. This results mainly from enhanced hot-electron trapping in the gate oxide and also from interface-trap generation. By applying an ECR-SiO/sub 2/ layer under the TEOS/O/sub 3/-oxide layer, tolerance against hot-carrier damage is improved to the level of MOSFETs without the TEOS/O/sub 3/ oxide. From ESR measurement results, it is found that the spin density of the ECR-SiO/sub 2/ film under the TEOS/O/sub 3/ oxide is two orders lower than that of the ECR-SiO/sub 2/ film only. It is suggested that the dangling bonds in the ECR-SiO/sub 2/ film effectively trap water diffusing from the water-containing overlayer. >

A Fingerprint Sensor with Impedance Sensing for Fraud Detection

A fingerprint sensor that integrates fraud detection and fingerprint sensing to prevent spoofing with a fake (artificial) finger is presented. Fingerprint identification using capacitive fingerprint sensing provides small user-authentication systems. For systems that need a higher level of security, fraud detection, which determines whether the sensed finger is alive or not, is necessary. Integrating fraud detection capability into a capacitive sensor is important because attempted fraud has to be detected at the same time that the fingerprint is captured. Various methods that use information about a finger, such as its electrical characteristics, optical characteristics or elastic characteristics, have been tried. Impedance-sensing is suitable from the viewpoint of using electrical signals. An impedance-sensing circuit should not increase the chip size nor degrade the quality of the captured fingerprint image. To meet these requirements, we propose an impedance-sensing scheme built into a capacitive sensor and implemented as a circuit and electrode without changing the chip size.

Evaluation of ESD hardness for fingerprint sensor LSIs

We evaluated the electrostatic discharge (ESD) hardness for some kinds of capacitive fingerprint sensor LSIs. In contact discharge tests, our sensor with the GND wall structure and another sensor with a GND demonstrated of ESD failure voltage above plusmn8 kV. On the other hand, in air discharge tests, ESD tolerance of our GND wall structure was over plusmn 20 kV, whereas that of the other GND structure was below plusmn 12 kV. It is evident from our findings that ESD immunity in the sensor LSIs obviously depends on the GND structure and our sensor LSI with the GND wall has the highest ESD tolerance.

Electrically separated two-axis MEMS mirror array module for wavelength selective switches

A novel two-axis MEMS mirror array module for wavelength selective switches feature a new electrode structure that reduces electrical interference between adjacent channels. The fabricated 50-channel mirror module has good characteristics satisfying system requirements.

Surface Cleaning of Gold Structure by Annealing during Fabrication of Microelectromechanical System Devices

We describe a technique for cleaning a gold surface using a dry process during the fabrication of microelectromechanical system (MEMS) devices. After exposure to oxygen plasma for ashing of the organic contaminants or etching of a sacrificial-layer film, the gold surface is oxidized. On such an oxidized surface, there are different incubation periods at different places, which give rise to nonuniform thickness in electroplating as well as in electrodeposition. A surface analysis by X-ray photoelectron spectroscopy (XPS) revealed that annealing at a temperature of over 260 °C causes oxygen to desorb from the gold oxide. The application of this cleaning technique before electroplating or electrodeposition leads to uniform growth.

Impedance-Sensing Circuit Techniques for Integration of a Fraud Detection Function Into a Capacitive Fingerprint Sensor

This paper describes techniques for an impedance-sensing circuit integrated into a capacitive fingerprint sensor to prevent spoofing with a fake finger. We have reported a sensor chip with an embedded impedance-sensing function. We proposed an impedance-sensing circuit that features current-to-voltage con- version using a unity gain buffer. Here, the design of the sensing circuit is discussed. The detectable impedance range and the sensitivity are analyzed within the impedance range for various human fingers. A test chip with the proposed circuit was fabricated using 0.5-μm CMOS/sensor processes. The results confirm that the difference in impedance between a real finger and a fake finger is detected without any degradation of the original characteristics of the fingerprint sensor chip.

Thick-dielectric formation and MOSFET reliability with spin-coating film transfer and hot-pressing technique for seamless integration technology

The formation of thick dielectrics by the spin-coating film transfer and hot-pressing (STP) technique is proposed for the fabrication of thick multilevel interconnects. Examination of the characteristics of 20-µm-thick dielectrics on 10-µm-thick line-and-space patterns shows sufficient planarization capability with little dependence on pattern density, which enables the fabrication of a double layer of thick interconnects. To investigate the influence of hot pressing in the STP process on LSIs, the hot-carrier degradation of n-channel metal oxide semiconductor field-effect transistors (MOSFETs) was evaluated. The lifetime of transconductance gm of STP samples was estimated to be over ten years, which is the same as that of samples prepared by the conventional technique of spin-coating. Moreover, the lifetime showed no dependence on pressure, temperature in hot pressing and thickness of dielectrics. These results confirm that the STP technique is applicable to the fabrication of thick interconnects and does not damage the underlying MOSFETs.