K. Ohhata

Design of a 32.7-GHz bandwidth AGC amplifier IC with wide dynamic range implemented in SiGe HBT

A wide-bandwidth automatic gain control (AGC) amplifier IC was developed using a self-aligned selective-epitaxial SiGe heterojunction bipolar transistor (HBT). A transimpedance load circuit was used, and its damping factor was optimized to achieve a wide bandwidth of 32.7 GHz. Capacitor peaking was introduced to the second variable-gain amplifier in order to obtain a wide gain dynamic range of 19 dB. The amplifier IC has a noise figure of 18 dB and an eye pattern at 25 Gb/s.

A wide-dynamic-range, high-transimpedance Si bipolar preamplifier IC for 10-Gb/s optical fiber links

A wide-dynamic-range, high-transimpedance preamplifier IC for 10-Gb/s optical fiber links was developed using a 0.3-/spl mu/m Si bipolar process. The preamplifier with a limiting amplifier enables a wide dynamic range from 16 /spl mu/App to 2.5 mApp and a high transimpedance of 1 k/spl Omega/ (2 k/spl Omega/ in the differential output mode). Moreover, careful circuit design achieves a transimpedance fluctuation of 0.5 dBR and an average equivalent input noise current density of 12 pA//spl radic/Hz. This preamplifier IC has the highest transimpedance of any Si bipolar preamplifier for 10-Gb/s operation. Thus, the preamplifier is suitable for 10-Gb/s short-haul optical fiber links and can be used to provide a low-cost system.

40 Gb/s 4:1 multiplexer and 1:4 demultiplexer IC module using SiGe HBTs

A 4:1 multiplexer and a 1:4 demultiplexer IC module were developed by using 0.2 /spl mu/m self-aligned selective-epitaxial-growth SiGe HBTs. For the data retiming, the multiplexer and the demultiplexer include a frequency divider that operates at over 40 GHz. 50-Gb/s operation for the multiplexer and 48-Gb/s operation for the demultiplexer were observed by measurements using on-wafer probes. We concluded that these modules, which mounted the IC on a ceramic substrate with a brass block, are applicable to transmitter and receiver functions of a 40-Gb/s optical transmission system.

43 Gb/s full-rate-clock 16:1 multiplexer and 1:16 demultiplexer with SFI-5 interface in SiGe BiCMOS technology

Fabricated in 0.18 /spl mu/m SiGe BiCMOS, 16:1 MUX and 1:16 DMUX MCMs equipped with an SFI-5 interface operate at 43 Gb/s. The on-chip CDR with external VCO recovers a full-rate clock with 2.5/spl deg/ RMS jitter from 2/sup 31/-1 PRBS. The SFI-5 bus also operates error-free at 2.7 Gb/s, and tolerates a /spl plusmn/6.6 Ul static skew.

45 GHz transimpedance 32 dB limiting amplifier and 40 Gb/s 1:4 high-sensitivity demultiplexer with decision circuit using SiGe HBTs for 40 Gb/s optical receiver

A preamplifier with 45 GHz bandwidth and 50.2 dB/spl Omega/ transimpedance gain, a limiting amplifier with 32 dB gain and 49 GHz bandwidth, and a 40 Gb/s 1:4 high-sensitivity demultiplexer (HS-DEMUX) combined with a decision circuit are for use in a 40 Gb/s optical receiver. The bandwidth in the preamplifier and the maximum gain at 40 GHz in the limiting amplifier are the best reported for any semiconductor technology. The 1:4 HS-DEMUX uses bit-rotation for byte-synchronization.

40 Gb/s analog IC chipset for optical receiver using SiGe HBTs

A preamplifier with 35 GHz bandwidth and 48.7 dB/spl Omega/ transimpedance gain, an automatic-gain-control (AGC) amplifier core with 31 GHz bandwidth, and a 40 Gb/s decision circuit are presented for future optical-transmission systems at a data rate of 40 Gb/s in global communication systems. A self-aligned selective-epitaxial SiGe-base heterojunction bipolar transistor is used to implement these circuits. This analog IC chipset meets the requirements for a 40 Gb/s optical receiver.

High-speed sensing techniques for ultrahigh-speed SRAMs

Two high-speed sensing techniques suitable for ultrahigh-speed SRAMs are proposed. These techniques can reduce a 64-kb SRAM access time to 71 approximately 89% of that of conventional high-speed bipolar SRAMs. The techniques use a small CMOS memory cell instead of the bipolar memory cell that has often been used in conventional bipolar SRAMs for cache and control memories of mainframe computers. Therefore, the memory cell size can also be reduced to 26 approximately 43% of that of conventional cells. A 64-kb SRAM fabricated with one of the sensing techniques using 0.5- mu m BiCMOS technology achieved a 1.5-ns access time with a 78- mu m/sup 2/ memory cell size. The techniques are especially useful in the development of both ultrahigh-speed and high-density SRAMs, which have been used as cache and control memories of mainframe computers. >

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-/spl mu/m/sup 2/ memory cells has been developed using 0.3-/spl mu/m BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAMs, which have been used as cache and control storages in mainframe computers. >

A low-jitter 16:1 MUX and a high-sensitivity 1:16 DEMUX with integrated 39.8 to 43GHz VCO for OC-768 communication systems

A fully integrated 39.8 to 43Gb/s OC-768 16:1 MUX/DEMUX chipset is implemented in a 0.18/spl mu/m BiCMOS process. Full-rate operation is realized with an on-chip VCO, and the chipset dissipates 11.6W. The measured output jitter of the packaged MUX is 630fs, and the sensitivity of DEMUX is 31 mV/sub PP/ single-ended with a BER <10/sup -12/.

40 Gb/s analog IC chipset for optical receivers-AGC amplifier, full-wave rectifier and decision circuit implemented using self-aligned SiGe HBTs

40 Gb/s analog IC chipset, an AGC amplifier, a full-wave rectifier and a decision circuit, for optical receivers were developed using SiGe HBT technology. The high performance SiGe HBT and optimized circuit configuration make possible an AGC amplifier with a 47.8 GHz bandwidth, a full-wave rectifier, and a decision circuit with 40 Gb/s operation.