Fumihiko Arakawa
Hitachi
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Publication
Featured researches published by Fumihiko Arakawa.
international solid-state circuits conference | 2000
Toru Masuda; K. Ohhata; Fumihiko Arakawa; Nobuhiro Shiramizu; Eiji Ohue; Katsuya Oda; R. Hayami; Masamichi Tanabe; Hiromi Shimamoto; M. Kondo; Takashi Harada; Katsuyoshi Washio
A preamplifier with 45 GHz bandwidth and 50.2 dB/spl Omega/ transimpedance gain, a limiting amplifier with 32 dB gain and 49 GHz bandwidth, and a 40 Gb/s 1:4 high-sensitivity demultiplexer (HS-DEMUX) combined with a decision circuit are for use in a 40 Gb/s optical receiver. The bandwidth in the preamplifier and the maximum gain at 40 GHz in the limiting amplifier are the best reported for any semiconductor technology. The 1:4 HS-DEMUX uses bit-rotation for byte-synchronization.
international solid-state circuits conference | 2004
Keiki Watanabe; Akio Koyama; T. Harada; Tatsuhiro Aida; Atsushi Ito; Tomoo Murata; Hiroyuki Yoshioka; Masahito Sonehara; Hiroki Yamashita; Kyosuke Ishikawa; Masahiro Ito; Nobuhiro Shiramizu; Takahiro Nakamura; K. Ohhata; Fumihiko Arakawa; Takeshi Kusunoki; H. Chiba; Tsutomu Kurihara; Mamoru Kuraishi
A fully integrated 39.8 to 43Gb/s OC-768 16:1 MUX/DEMUX chipset is implemented in a 0.18/spl mu/m BiCMOS process. Full-rate operation is realized with an on-chip VCO, and the chipset dissipates 11.6W. The measured output jitter of the packaged MUX is 630fs, and the sensitivity of DEMUX is 31 mV/sub PP/ single-ended with a BER <10/sup -12/.
international microwave symposium | 2001
K. Ohhata; Fumihiko Arakawa; Tom Masuda; Nobuhiro Shiramizu; Katsuyoshi Washio
40 Gb/s analog IC chipset, an AGC amplifier, a full-wave rectifier and a decision circuit, for optical receivers were developed using SiGe HBT technology. The high performance SiGe HBT and optimized circuit configuration make possible an AGC amplifier with a 47.8 GHz bandwidth, a full-wave rectifier, and a decision circuit with 40 Gb/s operation.
international solid-state circuits conference | 2002
Tetsuya Yamada; Naohiko Irie; J. Nishimoto; Yuki Kondoh; T. Nakazawa; K. Yamada; K. Tatezawa; T. Irita; S. Tamaki; H. Yagi; Mikio Furuyama; K. Ogura; Hiromi Watanabe; Ryuichi Satomura; K. Hirose; Fumihiko Arakawa; T. Hattori; Ikuo Kudo; Ikuya Kawasaki; Kunio Uchiyama
An application processor for 3G cellular phones, using 0.18 /spl mu/m CMOS technology, includes a single CPU and DSP core with an on-chip 128 kB SRAM. It enables software-based 15 frames/s MPEG-4 encoding of QCIF Simple @L1 at 70 MHz and 140 mW. Standby current of the processor is <10 /spl mu/A in a partially powered standby mode using separate power lines.
Archive | 1998
K. Ohhata; Fumihiko Arakawa; Takeshi Kusunoki; Hiroaki Nambu; Kazuo Kanetani; Kaname Yamasaki; Keiichi Higeta
Archive | 2005
Yoshihiro Hayashi; Fumihiko Arakawa; Takeshi Kusunoki; Satoshi Ueno
Archive | 2002
Kazuo Kanetani; Hiroaki Nambu; Kaname Yamasaki; Takeshi Kusunoki; Fumihiko Arakawa
Archive | 2002
Kazuo Kanetani; Hiroaki Nambu; Kaname Yamasaki; Takeshi Kusunoki; Keiichi Higeta; Kunihiko Yamaguchi; Fumihiko Arakawa
international solid-state circuits conference | 2004
Keiki Watanabe; Akio Koyama; Takashi Harada; Tatsuhiro Aida; Atsushi M. Ito; Tomoo Murata; Hiroyuki Yoshioka; Michihito Sonehara; Hiroki Yamashita; Kyosuke Ishikawa; Masahiro Ito; Nobuhiro Shiramizu; Takahiro Nakamura; K. Ohhata; Fumihiko Arakawa; Takuro Kusunoki; Hiroyuki Chiba; Tsutomu Kurihara; Mamoru Kuraishi
Archive | 2004
Keiki Watanabe; Akio Koyama; Takashi Harada; Tatsuhiro Aida; Atsushi Ito; Tomoo Murata; Hiroyuki Yoshioka; Masahito Sonehara; Hiroki Yamashita; Kyosuke Ishikawa; Masahiro Ito; Nobuhiro Shiramizu; Takahiro Nakamura; Kenichi Ohhata; Fumihiko Arakawa; Takeshi Kusunoki; Hiroyuki Chiba; Tsutomu Kurihara; Mamoru Kuraishi
