Nobuhiro Tanabe

A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme

With increase in the capacity of nonvolatile memories, the range of their use has been widening. A nonvolatile ferroelectric RAM (NVFRAM) based on a 1-transistor and 1-capacitor (1T/1C) memory cell has potential for fast-access time and small-chip size comparable with a DRAM. However, previously reported NVFRAMs are still slower than ordinary DRAMs, since driving a cell-plate line in NVFRAMs is slow. To avoid this, a non-driven cell plate line write/read scheme (NDP scheme) is presented which leads to NVFRAMs with as fast access time as DRAMs.

A ferroelectric capacitor over bit-line (F-COB) cell for high density nonvolatile ferroelectric memories

A ferroelectric capacitor over bit-line (F-COB) cell is proposed for high density nonvolatile ferroelectric memories (NVFRAMs). This memory cell with 0.7 /spl mu/m design rule was successfully fabricated using a newly-developed fabrication process, combining CMP and MOCVD techniques. Good ferroelectric properties of storage capacitor, having a remanent polarization of 15 /spl mu/C/cm/sup 2/ and leakage current density of 10/sup -6/ A/cm/sup 2/, have been realized without degradation in CMOS characteristics.

64 Kbit CMVP FeRAM macro with reliable retention/imprint characteristics

Packaged CMVP FeRAM chip reliability is evaluated for the first time. A 64 Kbit CMVP FeRAM macro is integrated with 0.35 /spl mu/m 3-level metallization CMOS logic devices. The ferroelectric properties of the PZT capacitor formed below 430/spl deg/C are not degraded even after plasma-SiON passivation. This is due to hydrogen barrier effect of TiN, and the high process damage immunity of the MOCVD PZT film. No failed bits are observed after a 240-hour retention/imprint period at temperatures between 25/spl deg/C and 150/spl deg/C with write/read voltages between 2.7 V and 5.5 V.

High tolerance operation of 1T/2C FeRAMs for the variation of cell capacitors characteristics

The operation of an FeRAM test chip is demonstrated with an 8 kbit cell array, sense amplifiers and other peripheral circuits for confirming the high tolerance of the 1T/2C FeRAM. The test chip is successfully fabricated by using a double layer metal process. The voltage difference to be amplified in data read for the 1T/2C FeRAM is 86 mV, which is large enough to operate, and four times larger than that for conventional 1T/1C FeRAM, after the cell capacitors characteristics are degraded and varied.

A high density 1T/2C cell with Vcc/2 reference level for high stable FeRAMs

A one transistor and two ferroelectric-capacitors (1T/2C) cell with Vcc/2 reference voltage level has been developed for high stable operation of ferroelectric nonvolatile memories (FeRAMs). The fixed reference voltage scheme creates a large sensing margin between the reference voltage and signal voltage, resulting into stable operation. 8F/sup 2/ (F: feature size) cell area for the 1T/2C cell is as small as a 1T/1C cell because smaller capacitance value of 1T/2C cell than that of 1T/1C is acceptable for a stable operation. The structure is promising for high density FeRAMs.

Scaling possibility of pzt capacitors for high density and low-voltage nvfram application

Abstract Scaling limit of the PZT capacitors for high-density and low-voltage Nonvolatile Ferroelectric RAM (NVFRAM) is described using the memory operation scheme for data read-out. The analysis is performed using the measured switching polarization characteristics of our 3 × 3μm2 PZT capacitors applicable to 1 Mbit NVFRAM. 16Mbit NVFRAM can be realized with simple shrinkage of our planar-type PZT capacitor without having to fabricate a stacked or trench capacitor.

Integration technology for ferroelectric memory

Abstract A 1T/2C FeRAM cell technology for high density applications is firstly discussed. 1T/2C FeRA cell with Vcc/2 reference voltage level has been successfully developed for high stable operation of FeRAMs. This structure is promising for high density FeRAMs. This paper also describes CMVP memory cell which is suitable for high performance CMOS logic embedded FeRAM. A PZT capacitor was firstly formed on metal(Al)/via(W) stacked plug using low-temperature MO-CVD process. CMVP memory cell is a candidate of embedded FeRAM in the future.

Individual cell measuring method for FeRAM retention testing

We propose a new testing methodology to predict the failure rate for long-term data retention of FeRAM chips. The individual retention time limit for each memory cell is determined by measuring the retention time dependence on the read signal voltage using a novel test system. From this experiment, we found that the retention time limit of each memory cell obeys a Gaussian distribution. We applied this method to the evaluation of 16 kbit FeRAM test chips, and successfully predicted the failure rates for long-term data retention time as the functions of temperature and writing voltage.