T. Kunio

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability. >

Three dimensional ICs, having four stacked active device layers

The four-layer-stacked master slice is proposed as a system application for 3-D ICs. The master slice consists of a programmable logic array for logic circuits, a CMOS gate array for I/O interface buffer circuits, and a CMOS SRAM. Fabrication technologies for the four-layer-stacked 3-D IC are described. Laser beam recrystallization was carried out for the formation of three SOI (silicon-on-insulator) layers in the 3-D IC. Recrystallization without cracks in both SOI and vertical isolation layers was accomplished by adjusting laser annealing conditions. Microprobe Raman spectroscopy data indicated that a tensile stress of (3-6)*10/sup 9/ dyne/cm/sup 2/ was present in each SOI layer. Surface planarization of the vertical isolation layer was carried out with a combination of polystyrene spin coating and dry etching. An initial surface roughness of about 1.7 mu m was successfully reduced to less than 500 A, and the planarized surface did not interfere with either recrystallization or photolithography. NMOSFETs and PMOSFETs, fabricated in the four-layer-stacked 3-D IC, have been successfully operated.<<ETX>>

A 30-ns 256-Mb DRAM with a multidivided array structure

A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25- mu m CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 mu m/sup 2/. Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm/sup 2/. >

A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme

With increase in the capacity of nonvolatile memories, the range of their use has been widening. A nonvolatile ferroelectric RAM (NVFRAM) based on a 1-transistor and 1-capacitor (1T/1C) memory cell has potential for fast-access time and small-chip size comparable with a DRAM. However, previously reported NVFRAMs are still slower than ordinary DRAMs, since driving a cell-plate line in NVFRAMs is slow. To avoid this, a non-driven cell plate line write/read scheme (NDP scheme) is presented which leads to NVFRAMs with as fast access time as DRAMs.

A dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film

A novel dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film is described. It is based on a new finding that threshold voltage (V/sub th/) depends on the concentration of nitrogen in the TiNx gate electrode. We found that a V/sub th/ shift as high as -110 mV is controlled by low-energy nitrogen-ion implantation (N I/I) into the titanium nitride film. By using this technology only for nMOSFETs, dual-metal gate CMOS devices are fabricated with a CMOS-process compatibility. A low V/sub th/ is achieved for both n- and pMOSFETs by combining N I/I and a low-doped channel structure.

A ferroelectric capacitor over bit-line (F-COB) cell for high density nonvolatile ferroelectric memories

A ferroelectric capacitor over bit-line (F-COB) cell is proposed for high density nonvolatile ferroelectric memories (NVFRAMs). This memory cell with 0.7 /spl mu/m design rule was successfully fabricated using a newly-developed fabrication process, combining CMP and MOCVD techniques. Good ferroelectric properties of storage capacitor, having a remanent polarization of 15 /spl mu/C/cm/sup 2/ and leakage current density of 10/sup -6/ A/cm/sup 2/, have been realized without degradation in CMOS characteristics.

A new three dimensional IC fabrication technology, stacking thin film DUAL-CMOS layers

A novel 3-D IC has been developed in which electrical function blocks of thin-film dual-active-device-layer (DUAL) CMOS ICs are bonded cumulatively. In the DUAL-CMOS ICs, pMOSFETs are stacked on nMOSFETs by using a laser beam annealing technique. By mechano-chemical polishing, the IC substrates are thinned, and then joined together. Operation of function blocks such as an inverter and ring oscillator stacked in the 3-D IC is confirmed.<<ETX>>

NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors

This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatile SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A V/sub dd//2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies.

An effective channel length determination method for LDD MOSFETs

We propose a definition of MOSFET effective channel length (L/sub EFF/), that provides a method of determining L/sub EFF/ as a constant, and external resistance (R/sub EXT/) virtually as a constant, even for lightly doped drain (LDD) transistors. A unified relationship between this L/sub EFF/ and MOSFET drive current (linear and saturation) that is common to a wide range of drain structures was confirmed. Therefore, the L/sub EFF/ is useful, not only for compact analytical models, but also as an index of MOSFET performance applicable to both single drain and LDD devices. The dependence of the channel length on the source/drain structure was clarified by introducing the concept of local contribution to channel length. The L/sub EFF/ varies, even if the metallurgical channel length is fixed, depending on the design of the source/drain.

Capacitor-on-metal/via-stacked-plug (CMVP) memory cell for 0.25 /spl mu/m CMOS embedded FeRAM

A capacitor-on-metal/via-stacked-plug (CMVP) memory cell was developed for 0.25 /spl mu/m CMOS logic embedded FeRAM. Using 445/spl deg/C MOCVD Pb(Zr,Ti)O/sub 3/ process, a ferroelectric capacitor is formed after CMOS logic fabrication. Thus, FeRAM can be embedded without changing any logic devices and processes. Furthermore, this technology enables cell size reduction (3.2 /spl mu/m/sup 2/ for 1T1C), minimum process damage on ferroelectric, and low manufacturing cost.