Nobutake Konishi

High performance low-temperature poly-Si n-channel TFTs for LCD

High-performance poly-Si TFTs were fabricated by a low-temperature 600 degrees C process utilizing hard glass substrates. To achieve low threshold voltage (V/sub TH/) and high field-effect mobility ( mu /sub FE/), the conditions for low-pressure chemical vapor deposition of the active layer poly-Si were optimized. Effective hydrogenation was studied using a multigate (maximum ten divisions) and thin-poly-Si-gate TFTs. The crystallinity of poly-Si after thermal annealing at 600 degrees C depended strongly on the poly-Si deposition temperature and was maximum at 550-560 degrees C. The V/sub TH/ and mu /sub FE/ showed a minimum and a maximum, respectively, at that poly-Si deposition temperature. The TFTs with poly-Si deposited at 500 degrees C and a 1000-AA gate had a V/sub TH/ of 6.2 V and mu /sub FE/ of 37 cm/sup 2//V-s. The high-speed operation of an enhancement-enhancement type ring oscillator showed its applicability to logic circuits. The TFTs were successfully applied to 3.3-in.-diagonal LCDs with integration of scan and data drive circuits. >

CMOS circuits for peripheral circuit integrated poly-Si TFT LCD fabricated at low temperature below 600 degrees C

CMOS shift registers, buffers, and gray-scale representation circuits for integrated peripheral drive circuits of poly-Si TFT LCDs were fabricated at temperatures below 600 degrees C on a glass substrate. The maximum operation frequency of the CMOS shift register was 1.25 MHz. The total power consumption of the 10 stage CMOS shift registers at a clock frequency of 46.8 kHz and a power supply voltage of 20 V was 10 mu W, which is three orders of magnitude smaller than that of 10-stage nMOS shift registers. The rise and fall times of the CMOS buffers were proportional to the inverse of the channel width, and the write time of the gray-scale representation circuits was proportional to the line memory capacitance. >

Inverse staggered poly-Si and amorphous Si double structure TFT's for LCD panels with peripheral driver circuits integration

Inverse staggered polycrystalline silicon (poly-Si) and hydrogenated amorphous silicon (a-Si:H) double structure thin-film transistors (TFTs) are fabricated based on the conventional a-Si:H TFT process on a single glass substrate. After depositing a thin (20 nm) a-Si:H using the plasma CVD technique at 300/spl deg/C, Ar/sup +/ and XeCl (300 mJ/cm/sup 2/) lasers are irradiated successively, and then a thick a-Si:H (200 nm) and n/sup +/ Si layers are deposited again. The field effect mobilities of 10 and 0.5 cm /sup 2//V/spl middot/s are obtained for the laser annealed poly-Si and the a-Si:H (without annealing) TFTs, respectively.

Analysis of current voltage characteristics of low-temperature-processed polysilicon thin-film transistors

The relationship between device performance and trap state density in polysilicon films was investigated. The density in the silicon energy gap was obtained by fitting the calculated on-state current versus gate voltage curve to the measured one for low-temperature ( >

Analysis of current-voltage characteristics in polysilicon TFTs for LCDs

An analytic model which can accurately calculate the characteristics of polysilicon TFTs was developed. The theoretical current-voltage curves were compared with measured data, and correlations with trap density in polysilicon film and device performance were investigated. Good agreement was obtained between theoretical and measured results. It was also found that on-current was improved by reducing the densities near the band edges in a forbidden gap. This effect was realized by optimizing the film deposition temperature or by using laser annealing. A hydrogenation effect reduced the density near the midgap, which improved off-current. The TFTs were successfully applied in grey-scale liquid-crystal displays (LCDs) with fully integrated drive circuits.<<ETX>>

26.1: Invited Paper: Materials and Components Optimization for IPS TFT‐LCDs

Materials and components for IPS (in-plane switching) -TFT-LCDS are optimized based on a basic analysis of the in-plane switching behavior of nematic liquid crystals. We have newly developed materials and components accessible for mass producible and commercially available IPS-TFT-LCDS. New phenomena unlike from that found in conventional TN-TFT-LCD cases, such as a higher holding ratio characteristic which is specific to the IPS mode, are found. An optimization procedure for a liquid crystal mixture and a color filter is reviewed. By using new materials and components, we have supplied an IPS-TFT-LCD module consisting of a common driver LSI whose driving voltage is 5 volts with a response speed of 60ms (rise+fall), almost comparable to that of conventional TN-TFT-LCDs. Finally, our recent development state toward a faster response speed of 25ms, which is applicable to a moving picture display, is discussed.

An LCD addressed by a-Si:H TFTs with peripheral poly-Si TFT circuits

Poly-Si TFTs of an inverted staggered structure are fabricated by peripheral laser annealing of plasma CVD a-Si:H films on SiN gate insulator. The side contact structure improves the TFT characteristics resulting in mobility of 20 cm/sup 2Vs and on/off ratio of 10/sup 6/. The fabrication process, carried out below 300/spl deg/C, is compatible with conventional a-Si TFT processes. The LCD using a switch matrix of poly Si TFTs has good performance and reduces the number of driver ICs by half.<<ETX>>

A 10-s doping technology for the application of low-temperature polysilicon TFTs to giant microelectronics

A bucket-type high-density (0.25-1.2-mA/cm/sup 2/) low-energy (500-2000 V) ion source was utilized for high-speed phosphorus doping directly into a thin polysilicon layer without cap SiO/sub 2/. Doping gas with He dilution was selected to reduce etching of polysilicon film. Excimer laser (XeCl, 8 mm*8 mm) pulse annealing was introduced to activate effectively the doped impurity. The combination of these techniques provided a practically low sheet resistance for the TFT source, drain, and gate with a short time doping. The low-temperature polysilicon TFT fabricated with a doping time of 10 s had characteristics comparable to those of that fabricated by a longer time doping or conventional ion implantation, showing the practicality of this technology and its promise for giant microelectronics. >

Indium Tin Oxide Dry Etching Using HBr Gas for Thin‐Film Transistor Liquid Crystal Displays

The dry etching technique for indium tin oxide (ITO) films has been investigated using HBr gas with a conventional parallel-plate-type reactive ion etching apparatus in order to fabricate ITO fine patterns for thin-film transistor addressed liquid crystal displays (TFT-LCDS). Etching rates of amorphous ITO and poly-ITO were almost the same, unlike the case with ITO wet etching. This demonstrates that the ITO etching rate using HBr gas is independent of the film characteristics. A scanning electron microscopy study of etched ITO films showed that the reaction products were not deposited on the sample surface, although the resist surface was roughened. Al films, which are the underlayers of ITO films for TFT-LCDs, were not etched by HBr gas only. Therefore, high ITO/Al selectivity can be obtained by HBr gas.

A novel technology for a-Si TFT-LCD's with buried ITO electrode structure

A novel process technology for a-Si TFT-LCDs with the buried ITO electrode (BI) structure was developed and applied to 10-in-diagonal LCD panels. By employing the BI structure, an aperture ratio of 29% was achieved in high resolution panels with a pixel size of 192 /spl mu/ and the pixel defect density was reduced to about one third of the conventional structure. The defect reduction effect of the BI structure was also confirmed theoretically. The BI structure provides significant advantages for high-performance TFT-LCDs. >