Takaya Suzuki

Excellent effects of hydrogen postoxidation annealing on inversion channel mobility of 4H-SiC MOSFET fabricated on (11 2 0) face

Effects of hydrogen postoxidation annealing (H/sub 2/ POA) on 4H-silicon carbide (SiC) MOSFETs with wet gate oxide on the (112~0) face have been investigated. As a result, an inversion channel mobility of 110 cm/sup 2//Vs was successfully achieved using H/sub 2/ POA at 800/spl deg/C for 30 min. H/sub 2/ POA reduces the interface trap density by about one order of magnitude compared with that without H/sub 2/ POA, resulting in considerable improvement of the inversion channel mobility to 3.5 times higher than that without H/sub 2/ POA. In addition, 4H-SiC MOSFET with H/sub 2/ POA has a lower threshold voltage of 3.1 V and a wide gate voltage operation range in which the inversion channel mobility is more than 100 cm/sup 2//Vs.

Measurement of Hall Mobility in 4H-SiC for Improvement of the Accuracy of the Mobility Model in Device Simulation

In order to construct a reliable parameter set for the physic al modeling of 4H-SiC, we are collecting and examining the physical parameters. The results of mobility measurement are presented and compared with the built-in model in the device simulator. The doping depe n nce of the electron mobility is in agreement with the built-in model, whereas that of the hole mobility is different from the built-in model in the higher doping region. Further, the anisotropy of the electron and hole mobility is investigated. The anisotropy of the electron mobility ) 0001 ( / ) 00 1 1 ( > < μ > < μ is about 0.83 and is in agreement with the built-in model. The anisotropy of the hole mobility is observed and it is estimated to be 1.15. To our knowledge, this is the first report of the anisotropy of the hole mobility in 4H-SiC. Introduction Silicon carbide devices have outstanding features, namely higher speed and lower loss than silicon devices. Among the many polytypes of SiC, 4H-SiC has attracted gre at att ntion as a candidate material for the next generation of power semiconductor devices, due t o the excellent physical properties such as the electric breakdown field and mobility. In order to r alize SiC devices that make the best use of the excellent physical properties, device simulati on technology of SiC is indispensable. However, the comprehensive and reliable parameter set for the physic al modeling of 4H-SiC for device simulators has not been reported. As a first step in the construction of a reliabl e par meter set for the physical modeling of 4H-SiC, we are collecting and examini ng the physical parameters systematically by fabricating test chips that consist of the el ments for physical property measurements. This paper is the first report on our ongoing research . The final goal of our research is the release of the comprehensive parameter set. In this paper, we present results of mobility measurement and compare them with the previous results. Experimental Figure 1 shows the top view of a test chip of the first lot. A prec ise patterning of contact, electrode and mesa by the mask process guarantees the precision of the physical property measurements. A test chip consists of elements (Hall bars and the square and clover shaped four terminal pattern) for mobility measurements and pin diodes for the impact ionization coefficient mea surements. Hall bars are tilted to the crystallographic axis every fifteenth degree in order to de ect the anisotropy of the mobility. Test chips were fabricated on 4H-SiC epitaxial wafers. For the measurements of the electron mobility, Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 443-446 doi:10.4028/www.scientific.net/MSF.433-436.443

4H-SiC MOSFETs on C(000-,1) Face with Inversion Channel Mobility of 127cm2/Vs

SiC power MOSFETs is a promising candidate for the normally-off type fast switching device in the next generation. However, the on-resistance of SiC power MOSFETs is almost the same as that of Si IGBTs, which is much higher than the calculated value. This is caused by the low channel mobility due to high interface trap density. Large improvement of channel mobility is expected for SiC power MOSFETs with low on-resistance. We have already reported that the inversion channel mobility of 4H-SiC MOSFETs fabricated on the C(000 _ ,1) face was 72cm 2 /Vs, which is higher than the Si(0001) face. In this paper, we have investigated the effects of gate-oxidation temperature and H2 post oxidation annealing on the Dit of n-type MOS capacitors and the inversion channel mobility of 4H-SiC MOSFETs fabricated on the C(000 _ ,1) face. The Dit is reduced and the inversion channel mobility is improved as the gate-oxidation temperature decreases. The inversion channel mobility of 4H-SiC MOSFETs with the gate-oxide film grown at 900°C is 118cm 2 /Vs. Furthermore, using H2 POA, we have succeeded in the inversion channel mobility as high as 127cm 2 /Vs. This means that the C(000 _ ,1) face would be capable of SiC power MOSFETs with the high blocking voltage. Introduction SiC power MOSFETs is a promising candidate for the normally-off type fast switching device in the next generation. At present, the on-resistance of SiC power MOSFETs becomes the almost same as that of Si IGBT, which is much higher than the value predicted from the physical properties of SiC. This is caused by the low channel mobility due to high interface trap density (Dit). Recently, we have reported that the inversion channel mobility as high as 198cm 2 /Vs for 4H-SiC MOSFETs fabricated on the (11 _ ,20) face were achieved using the pyrogenic oxidation and the H2 post oxidation annealing (POA)[1]. However, the breakdown field of the (11 _ ,20) face in 4H-SiC is approximately 75% of the Si(0001) face[2]. The (11 _ ,20) face might be disadvantageous for the high power MOSFETs. In contrast, the C(000 _ ,1)face has the largest oxidation ratio, which is approximately 70% of that of Si[3]. This enables large reduction of oxidation process time in SiC MOSFETs fabrication. Furthermore, the C(000 _ ,1) face has the same breakdown field as the Si(0001)face[4]. The C(000 _ ,1) face is considered to be suitable for power SiC MOSFETs. We Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 1417-1420 doi:10.4028/www.scientific.net/MSF.457-460.1417

High Inversion Channel Mobility of MOSFET Fabricated on 4H-SiC C(000-1) Face Using H2 Post-Oxidation Annealing

We have investigated pyrogenic oxidation and H 2 POA effects on MOS capacitors and the inversion channel mobility of SiC MOSFET on the C(000 _ ,1) face. Even MOSFET with the gate oxide formed using only pyrogenic oxidation can operate. The fie ld-e f ct channel mobility( FE) is 52cm /Vs. The H2 post oxidation annealing reduces the interface state density, a nd improves the channel mobility. As a result, we succeeded in the high FE of 72cm /Vs for the MOSFET fabricated on the C(000 _ ,1) face. This suggests that the C(000 _ ,1) face is capable of SiC power MOSFETs with the high blocking voltage. Introduction SiC power MOSFET is expected for switching device in the next g neration. The on-resistance of SiC power MOSFET is much higher than the theoretical value be caus of the low channel mobility due to high interface state density (D it). Recently, we have reported that the channel mobilities as high as 50cm /Vs and 160cm/Vs for 4H-SiC MOSFET fabricated on the (0001) face and the (11 _ ,20) face were achieved by use of the pyrogenic re-oxidation anneali g and the H2 post oxidation annealing (POA), respectively[1],[2]. The value of 50cm /Vs is low for the theoretical on-resistance of SiC power MOSFETs. The breakdown field of the ( 11 _ ,20) face in 4H-SiC is 75% of the (0001) face[3]. There also are many stacking faults in epit axial layers on the bulk substrate grown using a seed of the (11 _ ,20) face, which lead to the large leakage current [4]. In contrast , he C(000 _ ,1) face has superior properties such as larger oxidation rate a nd smaller surface roughness as compared with the Si(0001) face[5],[6]. Furthermore, it has no sta cking faults. Therefore, the C(000 _ ,1) face is considered to be suitable for power SiC MOSFETs with high channel mobility and high blocking voltage. However, there is no report that the SiC M OSFET on the C(000 _ ,1) face operates without the channel doping, which attains only very low c hannel mobility in 6H-SiC MOSFET with positive threshold voltage(V th)[7]. We have reported that pyrogenic oxidation and H 2 POA reduced the D it near the conduction band edge in band gap[6]. This means that there is a Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 567-570 doi:10.4028/www.scientific.net/MSF.433-436.567

Impact Ionization Coefficients of 4H-SiC

The electric field dependence and anisotropy of the impact ionization coefficients of 4H-SiC are investigated by means of the avalanche breakdown behavior of p + n diodes. The breakdown voltages as a function of doping density and the multiplication factors of a leakage current are obtained using p + n diode fabricated on ) 0001 ( and ) 0 2 11 ( 4H-SiC epitaxial wafers. The obtained impact ionization coefficients show large anisotropy; the breakdown voltage of a p + n diode on ) 0 2 11 ( wafer is 60% of that on ) 0001 ( wafer. We have shown that the anisotropy of the impact ionization coefficients is attributable to the anisotropy of saturation velocity originated from the electronic structure of 4H-SiC. Introduction The impact ionization coefficients are indispensable for predicting the breakdown voltages of power devices by device simulations. However, the reports of measurements of the impact ionization coefficient of 4H-SiC are limited, and they are not in agreement with one another [1,2]. Further, anisotropy of breakdown field of 4H-SiC was reported and it was shown that there is a significant reduction of the breakdown field when the electric field is applied perpendicular to the c-direction [3]. In order to understand avalanche breakdown behavior of a 4H-SiC power device, reliable parameter sets for the impact ionization coefficients are needed. In this paper, we present the parameter sets of impact ionization coefficients of 4H-SiC for 0001 and 0 2 11 directions that reproduce avalanche breakdown behavior of p + n diodes on ) 0001 ( and ) 0 2 11 ( epitaxial 4H-SiC wafers. We also discuss the origin of anisotropy of impact ionization coefficient of 4H-SiC based on the microscopic image of the impact ionization and the transport physics under high electric field. Experimental The breakdown voltages as a function of doping density and the multiplication factors of a leakage current are obtained using p + n diode fabricated on ) 0001 ( and ) 0 2 11 ( 4H-SiC epitaxial wafers. Figure 1 shows a cross section of the p + n diode and the measuring system for multiplication factors. The p + n junction of a diode is located between a p + -type epitaxial layer on p + -type substrate and an n-type epitaxial layer. The doping concentration of the n-type epitaxial layer was between 16 10 3× cm -3 and 17 10 2× cm -3 . Deep mesa for the isolation and the termination of pin diodes was formed using inductively coupled plasma (ICP) reactive ion etching in SF6 chemistries. Nickel was deposited for the contact area after the contact implantation and 1600C activation annealing, and sintered before the Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 673-676 doi:10.4028/www.scientific.net/MSF.457-460.673

In-Situ Monitoring of AlN Crystal Growth on 6H-SiC by the Use of a Pyrometer

We present an analysis of the pyrometer signals observed in AlN crystal growth on 6H-SiC taking into account the AlN emissivity. The pyrometer is sensitive to the initial stage of the crystal growth of AlN as well as the crystalline quality and the surface morphology of the substrate 6H-SiC. The analysis is applied to the classification of the electrical properties of the Al/AlN/6HSiC MIS structure.

Electrical Properties of pn Diodes on 4H-SiC(000-1) C-Face and (11-20) Face

We fabricated pn diodes on the 4H-SiC(000-1) C-face and (11-20) face. The epitaxial growth of the n-type drift layer was carried out in a low-pressure, horizontal hot-wall type CVD reactor under the optimized conditions for each substrate. The doping concentration and the thickness of the epitaxial layers were 1.6x10 16 cm -3 , 10μm and 4.0x10 15 cm -3 , 11μm for the (000-1) C-face and (11-20) face, respectively. The pn junction was fabricated by Al + ion implantation with multiple energy implantation (30-200kV) at 600°C subsequent to post-annealing at 1600°C for 5min in Ar ambient. In the case of the diode on the (000-1) C-face, we observed an abrupt avalanche breakdown, which is very similar to the case of the (0001) Si-face, at the theoretical breakdown voltage (1150V) calculated from the doping concentration and the thickness of the drift layer. On the other hand, a lower breakdown voltage (1200V) than the theoretical value (1900V) was observed in the case of the diode on the (11-20) face, and moreover, serious reverse leakage current was also observed. On the basis of the observation of the light emission under the reverse bias, we presume that the crystal defects, parallel to the <11-20> direction, lead to such a high leakage current under the reverse bias.

Influence of Stacking Faults on the I-V Characteristics of 4H-SiC Schottky Barrier Diodes Fabricated on the (11-20) Face

The influence of stacking faults (SFs) on I-V chara cteristics of 4H-SiC (11-20) Schottky barrier diodes (SBDs) fabricated on the epilayer gro wn n the substrate which was grown in [11-20] direction by sublimation method was investigated. The number of SF under the Schottky electrode was determined by KOH etching of (1-100) face crosssection. SFs were found to have severe influence on the leakage current of reverse characteri stic. The leakage current is increased even though a few SFs exist under the electrode. Introduction 4H-SiC (11-20) face has an advantage that the MOSFET fabricated on this face shows higher inversion channel mobility than that fabricated on (0 001) face [1,2]. This face, however, has an essential problem for commercial device applications that is no existence of large size (11-20) substrate, since the substrate is usually prepared by cutting ingot grown in the [0001] direction. A potential method for obtaining a large size (11-20) substrate is crystal growth in the [11-20] directio n by sublimation method. This method, however, has a prob lem that stacking faults (SFs) generates during the crystal growth [3]. In addition, SFs exist ing in the substrate are replicated in the epitaxial layer [4]. Silicon Carbide wafer contains various kind of cryst allographic defects such as micropipes, screw dislocations and SFs. The relationship between thes e d fects and the device performance for high power devices has been extensively studied. It is gen erally agreed that the micropipes and screw dislocations cause premature reverse breakdown of d iodes. Concerning the SF, its generation and influence on the stability of diode on-resistance du ring a continuous long term operation have been reported in recent study [5]. It has been recently suggested that the SF may deteri orat the reverse characteristics of Schottky barrier diode (SBD) fab ricated on (11-20) face [4]. However, no clear evidence for that has been reported so far. In this study, we have carried out a detailed investi gation of the influence of SFs on the reverse characteristics of SBD fabricated on (11-20) face. A nd we have found that the SF has severe influence on the reverse characteristics of (11-20) SBD. Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 925-928 doi:10.4028/www.scientific.net/MSF.433-436.925

X‐Ray Reflectivity Measurement of an Interface Layer Between a Low Temperature Silicon Epitaxial Layer and HF ‐ Treated Silicon Substrate

The analytical expressions for thickness and δ (δ=1-refractive index) of an interface layer from x-ray reflectivity measurements are obtained for an epitaxial layer/interface layer/Si substrate system. The contaminated interface layer between the defective epitaxial layer and Si substrate is detected by the x-ray reflectivity. The stacking fault density (SFD) in the epitaxial layer is correlated with the δ of the interface layer. There is a linear relation between the δ and oxygen concentration of the interface layers. The δ of the interface layer is less than that of Si which is mainly due to oxygen in the interface layer. The thicknesses of the interface layers are about 1.4 nm and they do not correlate with the SFDs in the epitaxial layer

Fabrication of Mesa-Type pn Diodes without Forward Degradation on Ultra-High-Quality 6H-SiC Substrate

Using our own substrate growth and epitaxial growth techniques, we fabricated a 1.4 kV mesa-type 6H-SiC pn diode with an ideal avalanche breakdown and without forward degradation. The 6H-SiC substrates were grown on Lely crystals with no micropipes and only minimal defects. A pn junction was fabricated by chemical vapor deposition (CVD) with p/n epitaxial films. We obtained 1.4 kV breakdown voltage, consistent with the ideal breakdown voltage calculated from the thickness (10μm) and doping concentration (2x10cm) of the drift layer. The application of 200 A/cm current stress in the forward direction produced no degradation, which is often observed with pn diodes on normal commercial substrates.