Yoshikazu Hosokawa

High performance low-temperature poly-Si n-channel TFTs for LCD

High-performance poly-Si TFTs were fabricated by a low-temperature 600 degrees C process utilizing hard glass substrates. To achieve low threshold voltage (V/sub TH/) and high field-effect mobility ( mu /sub FE/), the conditions for low-pressure chemical vapor deposition of the active layer poly-Si were optimized. Effective hydrogenation was studied using a multigate (maximum ten divisions) and thin-poly-Si-gate TFTs. The crystallinity of poly-Si after thermal annealing at 600 degrees C depended strongly on the poly-Si deposition temperature and was maximum at 550-560 degrees C. The V/sub TH/ and mu /sub FE/ showed a minimum and a maximum, respectively, at that poly-Si deposition temperature. The TFTs with poly-Si deposited at 500 degrees C and a 1000-AA gate had a V/sub TH/ of 6.2 V and mu /sub FE/ of 37 cm/sup 2//V-s. The high-speed operation of an enhancement-enhancement type ring oscillator showed its applicability to logic circuits. The TFTs were successfully applied to 3.3-in.-diagonal LCDs with integration of scan and data drive circuits. >

400 dpi integrated contact type linear image sensors with poly-Si TFT's analog readout circuits and dynamic shift registers

Four-hundred-dots-per-inch (dpi) sensors, including poly-Si thin-film-transistor (TFT) scanning circuits, and a-Si photodiodes fabricated on borosilicate glass have been developed. This contact-type image sensor contains TFT analog buffer amplifiers in the readout circuits. The scanning circuits can operate in a frequency range between 200 kHz and 1 MHz. The readout circuits incorporating TFT analog impedance converters decrease photodiode impedance by more than three orders of magnitude and improve the linearity between illumination intensity and the sensor output. High-resolution reading is achieved by the new contact-type linear image sensors with a storage time of 2 ms/line. >

A high-resolution active matrix using p-channel SOI TFTs

A high-quality silicon-on-insulator (SOI) layer with 3-in-diameter quartz substrate and connected silicon islands was fabricated by a radio-frequency-heated zone-melting-recrystallization method. The whole area was successfully recrystallized and 95% of the silicon layer had a

The Dielectrically Isolated High Voltage IC Technology

The dielectrically isolated high voltage IC technology was investigated. The diode structure with n+ buried layer as a channel stopper can achieve a high breakdown voltage for the same oxide thickness as compared with a conventional structure. The relations between diode parameters and the breakdown voltage were investigated and a control technique for the fixed charge density was applied to obtain the high voltage device. The dependence of the device characteristics on positions in the IC was studied and it was found that current gain of lateral pnp transisters depended on the positions significantly. The high voltage crossunder interconnection structure utilizing the n+ buried layer was developed. Using all these techniques, a 250 V analog IC and 350 V switching ICs for telecommunication were fabricated.