Noël Deferm

A 120GHz 10Gb/s phase-modulating transmitter in 65nm LP CMOS

This paper presents a 120GHz fully integrated 65nm low power (LP) CMOS transmitter that achieves data rates above 10Gb/s. At these high frequencies an extremely high bandwidth is available. This allows multi-gigabit-per-second communication which provides an answer to the ever-increasing demand for higher data rates in wireless systems. However, wideband modulation of a 120GHz signal in 65nm LP CMOS is a challenge.

A 100 GHz transformer-coupled fully differential amplifier in 90 nm CMOS

This paper proposes differential design techniques for W-band CMOS applications. Transformers are used as passive matching circuits, which provide numerous advantages compared to traditional matching circuits. Stabilization and gain improvement of the differential pair is achieved by a wideband neutralization technique. These techniques are combined in a fully differential amplifier which is successfully measured. To our knowledge, this is the first fully differential 100 GHz CMOS amplifier.

A 120 GHz Fully Integrated 10 Gb/s Short-Range Star-QAM Wireless Transmitter With On-Chip Bondwire Antenna in 45 nm Low Power CMOS

In this paper, a fully integrated D-band transmitter with on-chip dipole bondwire antenna implemented in 45 nm low-power CMOS is presented. The purpose of this 120 GHz wireless connector is to provide a high-speed short-range wireless communication link. On-chip frequency generation, insensitive to VCO pulling, is integrated together with a direct carrier quadrature vector modulator, ASK modulator, four-stage differential transformer-coupled power amplifier, and bondwire antenna. A 29-1-bit PRBS generator, capable of generating three parallel bit streams at a clock frequency of 8 GHz, is integrated on the same chip for measurement purposes. The transmitter is capable of efficiently generating BPSK, QPSK, and Star-QAM modulation formats. Data transmission over a distance up to 1 m is achieved for data rates as high as 2 Gb/s. For shorter distances, data rates up to 10 Gb/s are measured.

An Efficient High-Frequency Linear RF Amplifier Synthesis Method Based on Evolutionary Computation and Machine Learning Techniques

Existing radio frequency (RF) integrated circuit (IC) design automation methods focus on the synthesis of circuits at a few GHz, typically less than 10 GHz. That framework is difficult to apply to RF IC synthesis at mm-wave frequencies (e.g., 60-100 GHz). In this paper, a new method, called efficient machine learning-based differential evolution, is presented for mm-wave frequency linear RF amplifier synthesis. By using electromagnetic (EM) simulations to evaluate the key passive components, the evaluation of circuit performances is accurate and solves the limitations of parasitic-included equivalent circuit models and predefined layout templates used in the existing synthesis framework. A decomposition method separates the design variables that require expensive EM simulations and the variables that only need cheap circuit simulations. Hence, a low- dimensional expensive optimization problem is generated. By the newly proposed core algorithm integrating adaptive population generation, naive Bayes classification, Gaussian process and differential evolution, the generated low-dimensional expensive optimization problem can be solved efficiently (by the online surrogate model), and global search (by evolutionary computation) can be achieved. A 100 GHz three-stage differential amplifier is synthesized in a 90 nm CMOS technology. The power gain reaches 10 dB with more than 20 GHz bandwidth. The synthesis costs only 25 h, having a comparable result and a nine times speed enhancement compared with directly using the EM simulator and global optimization algorithms.

A 94GHz differential power amplifier in 45nm LP CMOS

This paper presents a 94GHz 4-stage differential transformer-coupled power amplifier with capacitive neutralization. The use of transformers results in excellent common mode isolation between the different stages while providing a good impedance match. The neutralized differential pairs guarantee differential stability. The PA was designed in a 45nm LP CMOS technology. An output 1dB compression point of +4dBm and a gain of 18dB was measured. The total chip area is 0.43mm2 and the active part consumes only 0.07mm2. The 3dB bandwidth is 14GHz. Power consumption is 120mW from a 1V supply, resulting in a peak PAE of 4.6%.

A 120GHz fully integrated 10Gb/s wireless transmitter with on-chip antenna in 45nm low power CMOS

In this paper a fully integrated D-band transmitter with on-chip dipole bondwire antenna implemented in 45nm low power CMOS is presented. On-chip frequency generation, insensitive to VCO pulling, is integrated together with a direct carrier quadrature vector modulator, ASK modulator, 4-stage differential transformer-coupled power amplifier and antenna. Digital baseband circuits are also integrated on the same chip. The chip is capable of generating QPSK and Star-QAM modulation formats. Data transmission over a distance up to 1m is achieved for data rates as high as 2Gb/s. For shorter distances, data rates up to 10Gb/s are measured.

CMOS at Millimeter Wave Frequencies

In the past, mm-wave integrated circuits were always designed in high-performance RF technologies due to the limited performance of the standard CMOS transistors [Hun88]. However, the continuous scaling of the CMOS process toward gate lengths of several tens of nanometers has resulted in a considerable increase of the MOSFET performance at mm-wave frequencies. Despite this evolution of the devices, the performance of a single MOSFET is still limited, so advanced analog and RF design techniques are required. Low available gain of the nMOS is one of the most restrictive properties which has a severe impact on all other design parameters. Another big problem is the parasitic Miller capacitance in the MOSFET which results in potentially unstable behavior. These problems, together with the techniques to analyze them and design techniques to solve them, are discussed in this chapter.

A 120-GHzWireless Link

The transmitters discussed in Chap. 5 have proven that high-data-rate wireless communication systems can be designed in a standard CMOS technology. However, due to the lack of proper mm-wave interfacing blocks and on-chip carrier generation, these chips could only operate in a laboratory environment. Also, only the design of the transmitter was considered, without careful analysis of the transmission channel and the receiver.

Millimeter-Wave Transmitters in CMOS

The limitations of millimeter (mm)-wave circuit design in CMOS were discussed in the previous chapters. Also, several design techniques were proposed to improve the behavior at device and circuit level. Applying these mm-wave CMOS design techniques is necessary to develop high-performance-integrated mm-wave transmitters, capable of processing data rates in the order of several Gb/s. Of course, these high data rates and carrier frequencies will also have an impact at system level. Therefore, traditional RF transmitter architectures should be reinvestigated and adjusted to meet the imposed specifications of high-speed wireless data communication while keeping the power consumption as low as possible.

Passive Devices: Simulation and Design

In the previous chapter it became clear that although the performance of CMOS technologies has increased over the past decade, the available gain at mm-wave frequencies is still limited. To maximize the performance of multistage differential amplifiers in which these transistors are integrated, accurate and low loss passive impedance matching structures are required. Chapter 4 will cover the detailed analysis of the concept of impedance matching and its impact on the performance of multistage differential amplifiers. In the first part of this chapter, the analysis and design of several passive matching circuits is discussed.