Anton de Graauw

A broadband differential cascode power amplifier in 45 nm CMOS for high-speed 60 GHz system-on-chip

A compact two-stage differential cascode power amplifier is designed and fabricated in 45 nm standard LP CMOS. The cascode configuration, with the common gate device placed in a separate P-well, provides reliable operating condition for the devices. The amplifier shows 20 dB small-signal gain centered at 60 GHz with a flat frequency response and 1-dB bandwidth of 10 GHz. The broadband large-signal operation is also ensured by providing constant load resistance to both stages over the entire band and coupling them with a dual resonance matching network. The chip delivers 11.2 dBm output power at 1-dB compression and up to 14.5 dBm power in saturation. The power amplifier operates with 2 V supply and draws 90 mA total current which results in 14.4% maximum PAE. The output third order intercept point is measured to be 18 dBm for two-tone measurement at 60 GHz with 0.5 GHz, 1 GHz and 2 GHz frequency separations.

A 21.7-to-27.8GHz 2.6-degrees-rms 40Mw frequency synthesizer in 45nm CMOS for mm-Wave communication applications

This work presents a 21.7-to-27.8GHz frequency synthesizer in a 45nm CMOS process that combines a tuning range of 24.8%, a residual phase modulation of 2.57°rms (with integrated phase noise from 100kHz to 100MHz), and a total power dissipation of 40mW. Combined with a frequency multiplier-by-two circuit and a divider-by-two circuit in a sliding-IF configuration, the PLL provides the four source frequencies required by the IEEE 802.15.3c 60GHz communication standard. In addition, the attained phase noise makes it suitable for microwave links with higher-order modulation schemes used as the back-bone for 3G/LTE base-station networks.

A 60GHz digitally controlled RF-beamforming receiver front-end in 65nm CMOS

Phased arrays form a crucial step towards high data rate 60GHz wireless communication. This paper presents a fully integrated digitally controlled 60GHz RF-beamforming receiver front-end in CMOS. Using digitally controlled active phase shifters, each path of the scalable architecture achieves 10dB power gain, 7.2dB noise figure, a 360° phase shift range in 22.5° steps at 61GHz, and a 3dB-bandwidth of 5.4GHz, while only dissipating 78mW in each path. Chip area is 1.6mm2.

A 94GHz differential power amplifier in 45nm LP CMOS

This paper presents a 94GHz 4-stage differential transformer-coupled power amplifier with capacitive neutralization. The use of transformers results in excellent common mode isolation between the different stages while providing a good impedance match. The neutralized differential pairs guarantee differential stability. The PA was designed in a 45nm LP CMOS technology. An output 1dB compression point of +4dBm and a gain of 18dB was measured. The total chip area is 0.43mm2 and the active part consumes only 0.07mm2. The 3dB bandwidth is 14GHz. Power consumption is 120mW from a 1V supply, resulting in a peak PAE of 4.6%.

Performance evaluation of 60 GHz WLAN antennas under realistic propagation conditions with human shadowing

In this paper, the evaluation of different 60 GHz WLAN antenna designs is presented. Based on ray tracing and human blockage the radio propagation in a living room scenario is modeled. Then simulated 3D antenna patterns of conventional and smart antennas are linked to the radio channel data. The performance of the antennas is compared in terms of the coverage probability within the living room.

A direct conversion quadrature transmitter with digital interface in 45 nm CMOS for high-speed 60 GHz communications

A compact 60 GHz direct conversion quadrature transmitter is designed and fabricated in 45 nm standard LP CMOS. The transmitter features an integrated power amplifier with continuous output level control and interfaces binary data signals with nominal peak-to-peak voltage swing of 300 mV. The highest measured modulation bandwidth is limited by the measurement setup to 4 GHz but is simulated to be as high as 10 GHz. In single sideband up-converting operation mode, the measured image suppression ratio is 22 dB with 36 dB of carrier suppression corresponding to approximately 8% EVM in the output signal constellation. The output RF frequency can be from 54 GHz to 66 GHz to accommodate several channels and the output power can be adjusted from −3 dBm to 10 dBm. The chip is operated from a 2 V supply and draws 180 mA current.

A 60GHz Miller Effect Based VCO in 65nm CMOS with 10.5% Tuning Range

This paper presents a 60 GHz voltage controlled oscillator implemented in conventional 65 nm CMOS technology. This VCO employs an alternative tuning system based on the Miller capacitance instead of conventional varactors. The presented VCO has a tuning range of 10.5 % and operates in the frequency range of 59.5 GHz to 66.1 GHz. It has an output power of -13 dBm and a phase noise of 80 dBc to -85 dBc/Hz @ 1 MHz over its entire range. The figure-of-merit (FOM) of this VCO is -162 dB.

A 120GHz fully integrated 10Gb/s wireless transmitter with on-chip antenna in 45nm low power CMOS

In this paper a fully integrated D-band transmitter with on-chip dipole bondwire antenna implemented in 45nm low power CMOS is presented. On-chip frequency generation, insensitive to VCO pulling, is integrated together with a direct carrier quadrature vector modulator, ASK modulator, 4-stage differential transformer-coupled power amplifier and antenna. Digital baseband circuits are also integrated on the same chip. The chip is capable of generating QPSK and Star-QAM modulation formats. Data transmission over a distance up to 1m is achieved for data rates as high as 2Gb/s. For shorter distances, data rates up to 10Gb/s are measured.

A broadband phased array antenna with wide angular coverage in a low-cost organic laminate package for 60-GHz wireless chipsets

This paper presents an eight-elements broadband phased array antenna embedded in a low-cost mainstream BT epoxy laminate package. Measurements and simulations of a 60 GHz module that includes the presented antenna array in combination with a phase controlled receiver chip demonstrate that this low-cost concept can provide 12dBi gain over 20% bandwidth and well controlled beam steering capabilities in the angular range of ±45° in the plane ε=0° and ±25° in the plane ε=90° and ε=45°.