Dixian Zhao

A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS

A 60-GHz dual-mode power amplifier (PA) is implemented in 40-nm bulk CMOS technology. To boost the amplifier performance at millimeter-wave (mmWave) frequencies, a new transistor layout is proposed to minimize the device and interconnect parasitics while the neutralized amplifier stage is co-optimized with input transformer to improve the power gain and stability. The transformer-based power-combining PA consists of two unit amplifiers, operating in Class AB for better back-off efficiency. To further reduce the power consumption and hence extend battery lifetime, one unit PA is tuned off in low-power mode. A switch is used to short the output of this non-operating unit PA to reduce the combiner loss and improve the efficiency. The PA achieves a measured saturated output power (PSAT) of 17.0 dBm (12.1 dBm) and 1-dB compressed power (P1dB) of 13.8 dBm (9.1 dBm) in the high-power (low-power) mode. The power-added efficiencies (PAEs) at PSAT and P1dB are 30.3% and 21.6% respectively for the high-power mode. Compared to Class A, the PA operating in Class AB shows 5.3% improvement in measured PAE at P1dB with no compromise in linearity. The PA with the power combiner only occupies an active area of 0.074 mm 2. The reliability measurements are also conducted and the PA has an estimated lifetime of 80613 hours.

A 60-GHz Outphasing Transmitter in 40-nm CMOS

This paper presents the analysis, design, and implementation of a 60-GHz outphasing transmitter in 40-nm bulk CMOS. The 60-GHz outphasing transmitter is optimized for high output power and peak power-added efficiency (PAE) while maintaining sufficient linearity. The chip occupies an active area of 0.33 mm2 and consumes 217 mW from a 1-V supply voltage, delivering 15.6-dBm linear output power with 25% PAE (PA). It achieves a 500-Mb/s 16QAM modulation with 12.5-dBm average output power and 15% average efficiency (PA) at an EVM of -22 dB. Mismatch compensation and phase correction are applied to further improve the average output power and efficiency by about 1.6 dB and 4%, respectively.

Synthesis of Integrated Passive Components for High-Frequency RF ICs Based on Evolutionary Computation and Machine Learning Techniques

State-of-the-art synthesis methods for microwave passive components suffer from the following drawbacks. They either have good efficiency but highly depend on the accuracy of the equivalent circuit models, which may fail the synthesis when the frequency is high, or they fully depend on electromagnetic (EM) simulations, with a high solution quality but are too time consuming. To address the problem of combining high solution quality and good efficiency, a new method, called memetic machine learning-based differential evolution (MMLDE), is presented. The key idea of MMLDE is the proposed online surrogate model-based memetic evolutionary optimization mechanism, whose training data are generated adaptively in the optimization process. In particular, by using the differential evolution algorithm as the optimization kernel and EM simulation as the performance evaluation method, high-quality solutions can be obtained. By using Gaussian process and artificial neural network in the proposed search mechanism, surrogate models are constructed online to predict the performances, saving a lot of expensive EM simulations. Compared with available methods with the best solution quality, MMLDE can obtain comparable results, and has approximately a tenfold improvement in computational efficiency, which makes the computational time for optimized component synthesis acceptable. Moreover, unlike many available methods, MMLDE does not need any equivalent circuit models or any coarse-mesh EM models. Experiments of 60 GHz syntheses and comparisons with the state-of-art methods provide evidence of the important advantages of MMLDE.

An E-Band Power Amplifier With Broadband Parallel-Series Power Combiner in 40-nm CMOS

This paper describes a fully integrated E-band power amplifier (PA) in 40-nm CMOS. The design and layout of the unit PA stage is optimized to achieve high output power while maintaining high power gain. A broadband parallel-series power combiner is proposed to provide the PA stage optimum load impedance across the complete E-band. The complete PA achieves a measured saturated output power of 20.9 dBm with more than 15-GHz small-signal -3-dB bandwidth and 22% power-added efficiency (PAE) at 0.9-V supply. The in-band variation of -1-dB compressed power (P1 dB) is only ±0.25 dB. This is the first reported silicon-based PA that covers both 71-76- and 81-86-GHz bands with uniform gain, output power, and PAE.

Transformer-Based Doherty Power Amplifiers for mm-Wave Applications in 40-nm CMOS

This paper presents a power amplifier (PA) topology to improve the back-off efficiency and the linearity of millimeter-wave (mm-wave) PAs without area overhead. In this paper, an asymmetrical series power combiner with LC tuning circuits is proposed to mimic the Doherty operation. Due to high back-off efficiency and high linearity behavior, the proposed Doherty topology well suits for E-band communication applications. Two transformer-based E-band PAs are designed and measured to demonstrate the proposed mm-wave Doherty concept. The first implementation achieves 16.2-dBm output power with a P1dB of 15.2 dBm using a 0.9-V supply. The second implementation demonstrates 21-dBm output power with a power-added efficiency (PAE) of 13.6% at a 1.5-V supply. The PAE at 6-dB power back-off is still as high as 7%.

14.1 A 0.9V 20.9dBm 22.3%-PAE E-band power amplifier with broadband parallel-series power combiner in 40nm CMOS

This paper reports a fully integrated 40nm CMOS PA that utilizes a broadband parallel-series power combiner to achieve an output power (POUT) of 20.9dBm with more than 15GHz small-signal 3dB bandwidth (BW-3dB) and 22% PAE at 0.9V supply. The in-band variation of P1dB is only ±0.25dB. This silicon-based PA covers both 71-to-76GHz and 81-to-86GHz bands with uniform gain, output power and PAE.

A 60GHz outphasing transmitter in 40nm CMOS with 15.6dBm output power

This paper presents a 60GHz transmitter (TX) based on the outphasing technique. It avoids amplifying variable-envelope signals and reconstructs the modulated signals by vector summing two constant-amplitude phase-modulated signals using an on-chip power combiner. The proposed design proves to have higher linear output power with better average efficiency compared to existing 60GHz solutions.

An Efficient High-Frequency Linear RF Amplifier Synthesis Method Based on Evolutionary Computation and Machine Learning Techniques

Existing radio frequency (RF) integrated circuit (IC) design automation methods focus on the synthesis of circuits at a few GHz, typically less than 10 GHz. That framework is difficult to apply to RF IC synthesis at mm-wave frequencies (e.g., 60-100 GHz). In this paper, a new method, called efficient machine learning-based differential evolution, is presented for mm-wave frequency linear RF amplifier synthesis. By using electromagnetic (EM) simulations to evaluate the key passive components, the evaluation of circuit performances is accurate and solves the limitations of parasitic-included equivalent circuit models and predefined layout templates used in the existing synthesis framework. A decomposition method separates the design variables that require expensive EM simulations and the variables that only need cheap circuit simulations. Hence, a low- dimensional expensive optimization problem is generated. By the newly proposed core algorithm integrating adaptive population generation, naive Bayes classification, Gaussian process and differential evolution, the generated low-dimensional expensive optimization problem can be solved efficiently (by the online surrogate model), and global search (by evolutionary computation) can be achieved. A 100 GHz three-stage differential amplifier is synthesized in a 90 nm CMOS technology. The power gain reaches 10 dB with more than 20 GHz bandwidth. The synthesis costs only 25 h, having a comparable result and a nine times speed enhancement compared with directly using the EM simulator and global optimization algorithms.

GASPAD: A General and Efficient mm-Wave Integrated Circuit Synthesis Method Based on Surrogate Model Assisted Evolutionary Algorithm

The design and optimization (both sizing and layout) of mm-wave integrated circuits (ICs) have attracted much attention due to the growing demand in industry. However, available manual design and synthesis methods suffer from a high dependence on design experience, being inefficient or not general enough. To address this problem, a new method, called general mm-wave IC synthesis based on Gaussian process model assisted differential evolution (GASPAD), is proposed in this paper. A medium-scale computationally expensive constrained optimization problem must be solved for the targeted mm-wave IC design problem. Besides the basic techniques of using a global optimization algorithm to obtain highly optimized design solutions and using surrogate models to obtain a high efficiency, a surrogate model-aware search mechanism (SMAS) for tackling the several tens of design variables (medium scale) and a method to appropriately integrate constraint handling techniques into SMAS for tackling the multiple (high-) performance specifications are proposed. Experiments on two 60 GHz power amplifiers in a 65 nm CMOS technology and two mathematical benchmark problems are carried out. Comparisons with the state-of-art provide evidence of the important advantages of GASPAD in terms of solution quality and efficiency.

A 60 GHz dual-mode power amplifier with 17.4 dBm output power and 29.3% PAE in 40-nm CMOS

A 60 GHz dual-mode power amplifier (PA) is implemented in 40-nm bulk CMOS technology. The PA consists of two unit PAs with a transformer-based power combiner at the output. To reduce the power consumption and hence extend battery life time, one unit PA is tuned off in low-power mode. A switch is employed to short the output of this off-state unit PA and thus improves the back-off efficiency. The PA achieves a saturated output power (PSAT) of 17.4 dBm with 29.3% PAE in high-power mode and a PSAT of 12.6 dBm with 19.6% PAE in low-power mode. The PA with the power combiner only consumes an active area of 0.074 mm2. The reliability measurements are also performed and the PA has an estimated lifetime of 80613 hours.