Noh-Jin Park

Off-device fault tolerance for digital imaging devices

Charged-coupled device (CCD) is one of the widely-used optical sensing device technologies for various digital imaging systems such as digital cameras, digital camcorders, and digital X-ray imaging systems. Pixels on a CCD may suffer from defective or faulty pixels due to numerous causes such as imperfect fabrication, excessive exposure to light radiation and sensing element aging to mention a few. As the use of high-resolution CCDs increase, defect and fault tolerance of such devices demands immediate attention. In this context, this paper proposes a testing and repair technique for defects/faults on such devices with inability of on-device fault tolerance, referred to as off-device fault tolerance. Digital image sensor devices such as CCD are by their nature, can not readily utilize traditional on-device fault tolerance techniques because each pixel on the device senses a unique image pixel coordinate. No faulty pixel can be replaced nor repaired by a sparse pixel as any displacement of an original pixel coordinate can not sense the original image pixel. Therefore, to effectively provide and enhance the reparability of such devices with inability of on-device fault tolerance, a novel testing and repair method for defects/faults on CCD is proposed based on the soft testing/repair method proposed in our previous work (Jin et al, 2003) under both single and clustered distribution of CCD pixel defects. Clustered fault model due to unwanted diffusion should be considered as practical model and for comparison purpose with single fault model. Also, a novel default/fault propagation model is proposed to effectively capture the on-device effects and faults off the device for an effectiveness and practicality of testing and repair process. The efficiency and effectiveness of the method is demonstrated with respect to the yield enhancement by the soft-testing/repair method under a clustered fault model as well as single fault model, as referred to as soft yield. Extensive numerical simulations are concluded.

Big Streaming Data Buffering Optimization

With increasing content of data that is being created around the globe, there are at times the need for analyzing the data real time. Few of the constraints that come with real-time analysis of such huge amounts of data are time and infrastructure. In cases where time of analyzing the data is a key factor, analysis cannot be done on all of the data that is being generated real-time as the speed of stream overweighs the speed of the processing the same. When time is not that important of a factor, it calls upon a very high end infrastructure to process heavy incoming traffic of data. In such scenarios where the entire population (real-time streaming data) cannot be analyzed and cases where the prior information about the population size is not available, Sampling of the population can be used as an effective technique and the processing can be done on sampled data by maintaining possible error at the least.

Fault tolerant memory design for HW/SW co-reliability in massively parallel computing systems

A highly dependable embedded fault-tolerant memory architecture for high performance massively parallel computing applications and its dependability assurance techniques are proposed and discussed in this paper. The proposed fault tolerant memory provides two distinctive repair mechanisms: the permanent laser redundancy reconfiguration during the wafer probe stage in the factory to enhance its manufacturing yield and the dynamic BIST/BISD/BISR (built-in-self-test-diagnosis-repair)-based reconfiguration of the redundant resources in field to maintain high field reliability. The system reliability which is mainly determined by hardware configuration demanded by software and field reconfiguration/repair utilizing unused processor and memory modules is referred to as HW/SW Co-reliability. Various system configuration options in terms of parallel processing unit size and processor/memory intensity are also introduced and their HW/SW Co-reliability characteristics are discussed. A modeling and assurance technique for HW/SW Co-reliability with emphasis on the dependability assurance techniques based on combinatorial modeling suitable for the proposed memory design is developed and validated by extensive parametric simulations. Thereby, design and Implementation of memory-reliability-optimized and highly reliable fault-tolerant field reconfigurable massively parallel computing systems can be achieved.

Regressive testing for system-on-chip with unknown-good-yield

This paper presents a testing method for electronic devices with no a-priori yield information. This problem is referred to as the unknown-good-yield (UKGY) problem. The UKGY problem of systems-on-chip (SoC) is discussed in this paper as SoCs are in general built with embedded intellectual property (IP) cores, each of which is procured from IP providers with no information on known-good-yield (KGY). In general, partial testing is a practical choice for assuring the yield of the product under the stringent time-to-market requirement in todays high density/complexity electronic devices such as SoCs built with deep submicron or nano technology. Therefore, an efficient and effective sampling technique is a key to the success of high confidence testing. An experimental characterization-based testing (referred to as ET) method for SoC has been proposed prior to this work, in which a stratified sampling method was employed based on environmental-based characterization and an experimental design technique to enhance the confidence level of the estimation of yield. The proposed testing method, referred to as regressive testing (RegT), in this paper exploits another method by using parameters (referred to as assistant variables (AV)) free from UKGY that determines the criteria to sample and test SoCs, and employs the regression analysis method to evaluate the yield with regard to confidence interval. A numerical simulation is conducted to demonstrate the efficiency and effectiveness of the proposed RegT in comparison with generic random testing method.

A Study of Heuristically-Based Parametric Performance Improvement/Optimization Algorithms for BigData Computing

Performance optimization for mapreduce computing in Hadoop platform is a tedious yet challenging problem due to the complexity of system organization with an extensive list of configuration parameters to be considered. In order to address and resolve this problem, various parameter optimization algorithms are proposed in this research from a naive exhaustive method to a random and a couple of heuristically-based greedy methods to vie with the exponentially nature of the search process for the possible best parameter setting. Extensive benchmark-based experiments have been conducted to validate the performance viability of the mapreduce computations by the benchmark programs such as TestDFSIO, TeraSort, to mention a couple. The experimental results demonstrate the proposed heuristically-based algorithms in greedy manner provide a promising answer to the problem of the research how to optimize the systems configuration parameter set at a computationally viable and feasible cost.

Modeling and analysis of repair and maintenance processes in Fault Tolerant Systems

This paper proposes a new model to evaluate the reliability, as a metric of the quality of fault tolerant systems that undergo repair and maintenance processes. The model is developed based on the markovian nature of repair and maintenance processes. The repair and maintenance processes are characterized with respect to mean time between failure, mean time between repair and mean time between maintenance. Simulation results are shown to demonstrate various co-effects of repair and maintenance processes on the reliability under the assumption of the proposed model.