Nooshin Saeidi

Humidity-to-Frequency Sensor in CMOS Technology With Wireless Readout

A remotely powered microsystem for humidity measurement is presented. The core of the active transponder consists of a humidity-to-frequency chip fabricated in a standard complementary metal-oxide-semiconductor (CMOS) technology, which contains both the humidity sensor and the readout circuit. The sensor is constructed using the polyimide passivation layer and the top metal layer available in the technology used. Power and data transmissions, to and from the chip, respectively, use the same pair of inductively coupled coils with a 13.56 MHz carrier. The humidity readout is transmitted by load shift keying to the external circuit. The chip is fabricated with commercial 0.6-μm CMOS technology and occupies an area of 4.8 mm2. The sensors capacitance exhibited good linearity against relative humidity (RH) levels from 15% to 85%. The normalized sensitivity is 0.073% per %RH at 35°C. The circuit level calibration limited spread from process and mismatch variations to about 10%. The chip has a total power consumption of 1.39 mW. The device has two purposes; either as a stand-alone wireless humidity sensor or to evaluate the hermeticity of packages, such as in biomedical implants.

A Capacitive Humidity Sensor Suitable for CMOS Integration

This paper describes the design, fabrication, and performance of a thin film humidity sensor fabricated in standard CMOS process, hence it may be combined with an integrated circuit. The sensor is based on a capacitance between interdigitated electrodes in the top metal layer and water adsorption in the polyimide layer. The design is optimized by analytical and then finite element models which show that, within the constraint of the CMOS structure, the sensitivity can be no greater than one third of the sensitivity of the polyimide alone. Experimental sensors were fabricated in-house before an improved design was fabricated in a commercial foundry. The different behavior of these sensors, despite their similar designs, leads to an investigation into the effects of fabrication process on the sensor linearity. Characterizing the polyimide film by contact angle, AFM and FTIR revealed that the difference in linearity of the response between the two sensors resulted from different etching techniques employed to pattern the film.

Technology for integrated circuit micropackages for neural interfaces, based on gold?silicon wafer bonding

Progress in the development of active neural interface devices requires a very compact method for protecting integrated circuits (ICs). In this paper, a method of forming micropackages is described in detail. The active areas of the chips are sealed in gas-filled cavities of the cap wafer in a wafer-bonding process using Au–Si eutectic. We describe the simple additions to the design of the IC, the post-processing of the active wafer and the required features of the cap wafer. The bonds, which were made at pressure and temperature levels within the range of the tolerance of complementary metal–oxide–semiconductor ICs, are strong enough to meet MIL STD 883G, Method 2019.8 (shear force test). We show results that suggest a method for wafer-scale gross leak testing using FTIR. This micropackaging method requires no special fabrication process and is based on using IC compatible or conventional fabrication steps.

Realization of an active book for multichannel intrathecal root stimulation in spinal cord injury — Preliminary results

After spinal cord injury, electrical stimulation of the roots inside the spinal column at the level of the cauda equina is a safe and effective way to regain some degree of control over lower body function, e.g. bladder and bowel management and leg movement. The success of current systems used for so-called intrathecal stimulation is limited by the low number of stimulation channels, which are in consequence of the maximum acceptable number of transdural cables. In order to overcome this limitation, we developed an active electrode with integrated electronics, providing four individual stimulation channels that requires one cable only. This paper outlines the different elements of the so-called active book with the emphasis on its preliminary construction and assembly.

An implantable humidity-to-frequency sensor in CMOS technology

This paper reports the development of a thin-film humidity sensor which is integrated as part of a standard CMOS chip. The sensor element is fabricated using the topmost polyimide layer and the top metal layer available in standard CMOS processes. The sensor has been made part of an integrated wireless device which converts its capacitance to an output frequency. Power transmission to, and data transmission from the device, use the same pair of inductively coupled coils. The humidity readout is transmitted by load shift keying. The chip was fabricated in a 0.6-µm CMOS technology and occupies an area of 4.8 mm2. The sensors capacitance exhibits good linearity against relative humidity (RH) levels from 15–85%. The normalized sensitivity is 0.073% per %RH at 37 °C. Power consumption is 1.19 mW. The device has two purposes: it can be a stand-alone wireless humidity sensor (the first wireless humidity sensor in standard CMOS technology reported to date) and it can be employed for evaluating the hermeticity of implantable biomedical micropackages.

The Effects of Fabrication Process on the Performance of a CMOS Based Capacitive Humidity Sensor

Introduction There has been a great deal of research on design and fabrication of thin film humidity sensors for a wide range of applications. Several groups have reported fabrication of these devices utilizing MEMS and CMOS processes [1-3]. Measuring the moisture induced changes in the dielectric constant of a moisture sensing film is a widely used method for humidity measurement which is also compatible with integrated circuit processing. However, the choice of a process compatible sensing film as well as the effects of processing steps on the performance of sensor have been major challenges for researchers. We report design and fabrication of a capacitive humidity sensor which can be integrated as part of a standard CMOS chip. However, we focus on the issues associated with process steps on the performance of the sensor.

Pattern Stamping Using Exfoliation for Heterogeneous Integration

The heterostructure composed of alternating layers is a promising both for high performance nano-electronic devices, and as a potential path for integrating optoelectronic devices. Recent advances in terms of performance and scalability of Germanium channel pMOSFET has been reported [1]. However, Ge layers are difficult to integrate with Si due to the misfit between the crystalline lattice parameters and the mismatch of the coefficient of thermal expansions (CTE). Low temperature direct wafer bonding is attractive as an alternative method for allowing the integration of latticemismatched materials. Moreover the wafer bonding technique are specifically sought to allow for the hybrid integration of optoelectronic integrated circuit such as vertical-cavity surface-emitting laser (VCSEL) [2]. We have reported the feasibility of transferring hydrogenimplanted germanium to silicon with a reduced thermal budget is investigated [3]. Based on the low thermal budget exfoliation (Smart-Cut) technique, we investigate the possibility of hybrid pattern stamping for heterogeneous integration. In the experiment hydrogen implanted Ge wafers were bonded directly to oxidized Si using radical activation technique. Prior to bonding, the Ge and oxidized Si wafers were cleaned in an SC1equivalent solution with ozone for Si and without ozone for Ge. After loading into the bonder wafers were activated and bonded in-situ under a pressure of 1kN applied for 5 minutes at a chamber pressure of 10 mbar. The wafers were annealed in-situ at 100°C for 1 hour with an applied pressure of 500N in vacuum followed by an ex-situ anneal at 130°C for 24 hours and additionally 300°C for several minutes. After two-step anneal thin Ge layer transferred on oxideized Si wafer. Bonded interfaces were imaged by SAM. Then implanted Ge with 500um pitch pattern was directly bonded to oxidized Si wafer using oxygen radical activation technique. Figure 1 illustrates the germanium layer was transferred to the host silicon wafer without interface degradation after 300°C short time anneal. It shows that the bond strength of oxygen radical activated sample was high enough to allow pattern stamping in donor germanium wafer after 130°C long time anneal. The successful pattern stamping from a donor germanium to a host silicon wafer has been demonstrated. Figure 2 shows that patterned substrate can be successfully transferred at low temperature, which can be used alignment mark for additional stamping using IR alignment. This low temperature process is suitable for heterogeneous integration for hybrid CMOS platform or hetro-optoelectronics. Fig. 1. Buried interfaces after layer transfer.