Norihide Kashio

High-Speed and High-Reliability InP-Based HBTs With a Novel Emitter

This paper describes InP HBTs with a novel emitter simply consisting of a degenerately doped n+-InGaAs layer and an undoped InP thin layer. An n+-InP layer is not necessary because the quasi-Femi level in the n+-InGaAs layer is high enough to exceed the conduction band discontinuity between the n+ -InGaAs layer and the undoped InP layer. In the proposed structure, a thin ( ~ 10 nm) ledge structure can easily be fabricated by etching the n+-InGaAs layer. The fabricated HBTs with a 15-nm-thick ledge structure provide a high collector current density of over 6 mA/¿m2 . There is almost no degradation of current gain, although the emitter width is reduced to as small as 0.5 ¿m. The HBTs also exhibit an ft of 324 GHz at a collector current density of 5.5 mA/¿m2, which is comparable with that of HBTs with a conventional emitter consisting of an n+ -InGaAs layer, an n+-InP layer, and an n-InP layer. From the results of accelerated life tests, the activation energy of the degradation in HBTs is estimated to be around 1.8 eV, and the extrapolated mean time to failure is estimated to be over 108 h at a junction temperature of 125°C.

Highly Reliable Submicron InP-Based HBTs with over 300-GHz ft

We have developed 0.5-μm-emitter InP-based HBTs with high reliability. The HBTs incorporate a passivation ledge structure and tungsten-based emitter metal. A fabricated HBT exhibits high collector current density and a current gain of 58 at a collector current density of 4mA/μm2. The results of dc measurements indicate that the ledge layer sufficiently suppresses the recombination current at the emitter-base periphery. The HBT also exhibits an ft of 321GHz and an fmax of 301GHz at a collector current density of 4mA/μm2. The ft does not degrade even though the emitter size is reduced to as small as 0.5μm×2μm. The results of an accelerated life test show that the degradation of dc current gain is due to thermal degradation of the interfacial quality of semiconductors at the passivation ledge. The activation energy is expected to be around 1.5eV, and the extrapolated mean time to failure is expected to be over 108 hours at a junction temperature of 125°C. These results indicate that this InP HBT technology is promising for making over-100-Gbit/s ICs with high reliability.

Monolithic Integration of InP HBTs and Uni-Traveling-Carrier Photodiodes Using Nonselective Regrowth

This paper describes the monolithic integration of InP HBTs and uni-traveling-carrier photodiodes (UTC-PDs) by nonselective regrowth. HBTs are fabricated from nonselectively regrown device layers and UTC-PD subcollector layers, which are grown first on a 3-in InP substrate. This makes it possible to optimize the layer design for the HBTs and UTC-PDs independently and minimize the interconnection between them. The fabricated HBTs have a collector thickness of 200 nm, and they show an ft of 260 GHz and an fmax of 320 GHz at a collector current density of 2.5 mA/mum2. The standard deviations of the ft and fmax across the wafer are 1.7% and 4.4%, respectively. The length of the interconnection between the HBTs and UTC-PDs can be made as small as 10 mum without any degradation of the regrown-HBT performance. The UTC-PDs fabricated on the same wafer exhibit a 3-dB bandwidth of 100 GHz and an output voltage of 1.0 V. There is no drawback in the performance of either device, as compared with that of discrete devices. We also demonstrate 100-GHz optical-input divide-by-two optoelectronic integrated circuits (OEICs) consisting of InP HBTs and a UTC-PD using this technique. These results indicate that the nonselective regrowth is promising for application toward over 100-Gb/s OEICs.

Over 450-GHz f t and f max InP/InGaAs DHBTs With a Passivation Ledge Fabricated by Utilizing SiN/SiO 2 Sidewall Spacers

This paper describes InP/InGaAs double heterojunction bipolar transistor (HBT) technology that uses SiN/SiO2 sidewall spacers. This technology enables the formation of ledge passivation and narrow base metals by i-line lithography. With this process, HBTs with various emitter sizes and emitter-base (EB) spacings can be fabricated on the same wafer. The impact of the emitter size and EB spacing on the current gain and high-frequency characteristics is investigated. The reduction of the current gain is <;5% even though the emitter width decreases from 0.5 to 0.25 μm. A high current gain of over 40 is maintained even for a 0.25-μm emitter HBT. The HBTs with emitter widths ranging from 0.25 to 0.5 μm also provide peak ft of over 430 GHz. On the other hand, peak fmax greatly increases from 330 to 464 GHz with decreasing emitter width from 0.5 to 0.25 μm. These results indicate that the 0.25-μm emitter HBT with the ledge passivaiton exhibits balanced high-frequency performance (ft = 452 GHz and fmax = 464 GHz), while maintaining a current gain of over 40.

Improvement of High-Frequency Characteristics of InGaAsSb-Base Double Heterojunction Bipolar Transistors by Inserting a Highly Doped GaAsSb Base Contact Layer

This letter presents InP/GaAsSb/InGaAsSb/InP double heterojunction bipolar transistors (DHBTs) with a highly doped base contact layer. In order to reduce the base contact resistivity, a 3-nm-thick highly doped GaAsSb contact layer is inserted between the InP emitter and 17-nm-thick composition- and doping-graded InGaAsSb base. Fabricated DHBTs with a 0.25-μm emitter show a current gain of 32 and a high open-base breakdown voltage BVCEO of 5.2 V. The DHBTs also exhibit fT/fmax = 513/637 GHz at a collector current density of 9.5 mA/μm2 and VCE = 1 V. The fmax is higher by 124 GHz than that for InP/InGaAsSb DHBTs without the GaAsSb contact layer. These results indicate that the use of the GaAsSb/InGaAsSb base structure is very effective in improving fmax.

Composition- and Doping-Graded-Base InP/InGaAsSb Double Heterojunction Bipolar Transistors Exhibiting Simultaneous \(f_{t}\) and \(f_{\textrm {max}}\) of Over 500 GHz

We demonstrate composition- and doping-graded-base InP/InGaAsSb double heterojunction bipolar transistors (DHBTs) with a passivation ledge fabricated in a self-aligned process with i-line lithography. We obtained a high current gain of 52 and high breakdown voltage of 5 V for 0.2-μm-emitter DHBTs featuring 30-nm-thick composition- and doping-graded InGaAsSb base and 100-nm-thick InP collector. The HBTs exhibit an ft of 501 GHz and an fmax of 503 GHz at a collector current density of 10.6 mA/μm2 .

Emitter layer design for high-speed InP HBTs with high reliability

We investigated the influence of emitter doping level on the performance for high-speed InP HBTs with high reliability. The HBTs show high current gain and excellent reliability characteristics under stress current density of 5 mA/mum2.

0.3 V/sub pp/ single-drive push-pull InP Mach-Zehnder modulator module for 43-Gbit/s systems

We have developed an ultra low driving voltage (255 mVpp) and very compact InP-based n-i-n Mach-Zehnder modulator module. The module has a built-in driver IC. 43 Gbit/s single-drive push-pull operation is demonstrated using this compact module

Up to 80-Gbit/s operations of 1:4 demultiplexer IC with InP HBTs

We report up to 80-Gbit/s operations of a 1:4 demultiplexer (DMX) IC with InP HBTs of f/sub T/=292 GHz, f/sub max/=308 GHz. The circuit features are 1) the multiphase clock (MPC) architecture to suppress the increase of the power consumption, and 2) the high collector current density of 5.0 mA//spl mu/m/sup 2/ for the fastest circuit blocks. To measure the IC at over 50 Gbit/s where available data pulse pattern generators (PPGs) are few, we constructed two-types of data PPGs, which were a purely electrical PPG (E-PPG) and an optoelectronic PPG (OE-PPG). With these technologies, we successfully confirmed the operations up to 80 Gbit/s for the 1:4 DMX IC.

Reliability study on InP/InGaAs emitter-base junction for high-speed and low-power InP HBT

The reliability of sub-micrometers InP-based heterostructure bipolar transistors (HBTs), which are being applied in over-100-Gbit/s ICs, was examined at high current injection conditions. These HBTs had a ledge structure and an emitter electrode consisting with a refractory metal of W, which suppressed surface degradation and metal diffusion, respectively. We conducted bias-temperature (BT) stress tests in several stress conditions of current densities, Jc, up to 10 mA/μιη2 in order to investigate the stability of InP/InGaAs emitter-base (E-B) junction. At 10 mA/μιη2 operation with the junction temperature of 210 °C, dc current gain, ß, was stable for 1000 h. The activation energy for the reduction of β, however, decreased to 1.1 eV, which is suggesting the degradation of the emitter-base (E-B) junction. For the reliability of sub-micrometer, high-speed and low-power InP HBTs at high current densities, stability around the E-B junction has become more dominant.